JPS6453255A - Data processor - Google Patents

Abstract

PURPOSE:To avoid the malfunctions and the stall of a data processor by checking a counter value in the timing where lock release is clear at the end time of execution of an instruction or the end time of event processing. CONSTITUTION:A 1st means of an instruction control circuit 1 outputs the instruction execution end signals 14 and 15 at the end of execution of an instruction. Then a 2nd means of a memory control circuit 2 outputs a clock processing signal 11 when lock request processing succeeds and also an unlock processing signal 12 when unlock processing is carried out respectively. A lock control and check circuit 3 checks whether the signal 11 serving as the output of the 2nd means and the signal 12 are outputted in the same frequency or not based on the output of the 1st means and in the timing where a fact that the lock is released is clear. Thus it is possible to detect the conflict of the lock control and to avoid the malfunctions and the stall of the data processor.