JPS6452006U - - Google Patents
Info
- Publication number
- JPS6452006U JPS6452006U JP14378887U JP14378887U JPS6452006U JP S6452006 U JPS6452006 U JP S6452006U JP 14378887 U JP14378887 U JP 14378887U JP 14378887 U JP14378887 U JP 14378887U JP S6452006 U JPS6452006 U JP S6452006U
- Authority
- JP
- Japan
- Prior art keywords
- programmable controller
- host computer
- setting device
- analysis means
- host
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004458 analytical method Methods 0.000 claims 3
- 230000005540 biological transmission Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Information Transfer Systems (AREA)
- Programmable Controllers (AREA)
Description
第1図はこの考案の一実施例を示すプログラマ
ブルコントローラのハード構成を示すブロツク図
、第2図はその動作を示すフローチヤートである
。
図において、10は上位リンクモジユール、1
1は直列入出力制御装置、12はデイツプスイツ
チである。
FIG. 1 is a block diagram showing the hardware configuration of a programmable controller showing an embodiment of this invention, and FIG. 2 is a flowchart showing its operation. In the figure, 10 is the upper link module, 1
1 is a serial input/output control device, and 12 is a dip switch.
Claims (1)
グラマブルコントローラにおいて、上位コンピユ
ータに対する応答遅延時間に対応する信号を設定
する設定器と、該設定器の設定信号を解析する解
析手段と、該解析手段の出力に基づいて上位機種
へのデータ送信を所定時間遅延させる遅延手段と
を有することを特徴とするプログラマブルコント
ローラ。 In a programmable controller capable of data communication with a host computer, a setting device sets a signal corresponding to a response delay time to the host computer, an analysis means for analyzing the setting signal of the setting device, and an analysis method based on the output of the analysis means. A programmable controller comprising: delay means for delaying data transmission to a host model for a predetermined period of time.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1987143788U JP2545820Y2 (en) | 1987-09-22 | 1987-09-22 | Programmable controller |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1987143788U JP2545820Y2 (en) | 1987-09-22 | 1987-09-22 | Programmable controller |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6452006U true JPS6452006U (en) | 1989-03-30 |
JP2545820Y2 JP2545820Y2 (en) | 1997-08-27 |
Family
ID=31410924
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1987143788U Expired - Lifetime JP2545820Y2 (en) | 1987-09-22 | 1987-09-22 | Programmable controller |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2545820Y2 (en) |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS54527A (en) * | 1977-06-03 | 1979-01-05 | Hitachi Ltd | Control circuit for terminal unit |
JPS60117988A (en) * | 1983-11-30 | 1985-06-25 | Yokogawa Hewlett Packard Ltd | Video signal measurement device |
JPS6194951U (en) * | 1984-11-20 | 1986-06-19 | ||
JPS62117006A (en) * | 1985-11-18 | 1987-05-28 | Omron Tateisi Electronics Co | Programmable controller |
-
1987
- 1987-09-22 JP JP1987143788U patent/JP2545820Y2/en not_active Expired - Lifetime
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS54527A (en) * | 1977-06-03 | 1979-01-05 | Hitachi Ltd | Control circuit for terminal unit |
JPS60117988A (en) * | 1983-11-30 | 1985-06-25 | Yokogawa Hewlett Packard Ltd | Video signal measurement device |
JPS6194951U (en) * | 1984-11-20 | 1986-06-19 | ||
JPS62117006A (en) * | 1985-11-18 | 1987-05-28 | Omron Tateisi Electronics Co | Programmable controller |
Also Published As
Publication number | Publication date |
---|---|
JP2545820Y2 (en) | 1997-08-27 |
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