JPS62117006A - Programmable controller - Google Patents

Abstract

PURPOSE:To increase the response speed at the side of a programmable controller when viewed from a host equipment by supplying the data on the programmable controller main body stored in a data communication unit to the host equipment when this equipment delivers a request for transmission of data. CONSTITUTION:The data are supplied and stored previously into a data communication unit 21 from a PC main body 20 very time the main body 20 finishes a single scan. Then the unit 21 produces the response out of the stored data when a command is received from a host computer. This response is sent to the host computer. Thus it is possible to send immediately the data corresponding to the command to the host computer from the unit 21 even though the main body 20 is already through with a single scan before the supply is over with the command given from the host computer.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a programmable controller including a programmable controller main body and a data communication unit connected to the programmable controller main body.

(Summary of the Invention) A programmable controller according to the present invention includes a programmable controller main body, a data communication unit connected to the programmable controller main body,
Each time the programmable controller main body performs one scan, the data communication unit reads and stores data in the programmable controller main body, and when the higher-level device outputs a data transmission request, the data communication unit reads and stores the data stored in the programmable controller main body. Data from the controller main body is outputted and supplied to the host device, thereby improving the response speed of the programmable controller as viewed from the host device.

(Prior Art) Conventionally, a programmable controller (hereinafter abbreviated as PC) has a link unit and is capable of exchanging data with a host computer (host device) via the link unit. It has been known.

However, in conventional PCs equipped with such a link unit, the CPU' (Central Processing Unit) installed in the PC body communicates with the host computer via the link unit while sequentially controlling the controlled devices. Therefore, when a controlled device is controlled at high speed by the PC main body, there is an inconvenience that the communication function deteriorates.

Therefore, in recent years, instead of such a link unit, a data communication unit with a dedicated communication processor has been introduced into the PC.
A device has been developed that is attached to the main body and allows all communication-related processing to be processed collectively on the data communication unit side.

FIG. 6 is a block diagram showing an example of a PC having such a data communication unit.

The PC shown in this figure includes a PC main body 1 and a data communication unit 2. Even when the PC main body 1 is performing high-speed sequence control of the controlled Ili device, the data communication unit 2 is activated in parallel with this operation. It is configured to communicate with a host computer.

In this case, the PC body 1 controls the controlled tiam device in sequence according to the user program, and the CPU 3
, system program memory 4, user program memory 5, I10 controller (input/output controller) 6, I10 memory (input/output memory) 7, and synchronization 1/
F (synchronous interface) 8.

Further, when the data communication unit 2 is supplied with a data transmission request from the host computer via the line 9,
After holding this and completing one scan of the PC main body 1,
The communication controller 10 receives data from the PC main body 1 and sends it to the host computer.
, a system program memory 11 , and a buffer memory 12 .

It is configured to include a CPU 13 and a synchronous 1/F 14.

These PC main body 1 and data communication unit 2 operate as described below.

First, when the power is turned on to the PC, the CPL of the PC main unit 1
J3 executes step ST1 of the flowchart shown in FIG. 7 according to the system program to initialize each part of the circuit.

Next, CPtJ3 stores I10 memory 7 in step ST2.
After that, in step ST3, the user program is executed, and the necessary data, e.g. Data A.

B and C are determined and set in the I10 memory 7, and at the same time, the 110 controller 6 is controlled according to the processing procedure specified in the user program, and the RIll1 equipment connected to this I10 controller 6 is sequence-controlled. .

Next, in step ST4, the CPU 3 performs a synchronization service-like process, for example, if the data communication unit 2 has issued a data transfer request, it outputs a synchronization signal and performs the synchronization 1.
CPU1 of data communication unit 2 via /F8.14
3 to open the bus on the PC main body 1 side, and operate again when a synchronization release command is supplied from the data communication unit 211N to execute other synchronization service-like processing, and then proceed to step ST2. Go back and repeat the above operations.

Also, when this PC1,: power is turned on, the data communication unit 2 is turned on together with the PC main body 1, and the CPU
3 initializes each part of the circuit on the data communication unit 2 side, and then performs command reception processing in step ST5.

When the CPU i 3 receives a command such as a data transmission request from the host computer, it receives the command via the communication controller 10 and proceeds to step ST6.
The processing corresponding to this command, for example, if the command is a data transmission request, the PC body 1 will wait until the synchronization signal is output, and then generate a synchronization signal when this synchronization signal is output, Sync this 1/F14.8
The bus is supplied to the CPU 3 on the PC main body side via the CPU 3, and the bus on the PC main body 1 side is opened.

Next, the CPLJ13 accesses the I10 memory 7 on the PC body 1 side via the 1911/F14, 8, and sends the data indicated by the data transmission request, for example, data A.
, B, and C and store them in the buffer 7 memory 12, a synchronization release signal is generated and this is sent to the PC main body 1.
side CP (supply to J3).

Next, the CPU 13 generates a response in a predetermined format based on the data A, B, and C stored in the buffer memory 12 in step ST7, and transmits the response via the communication controller 10 to the host computer in step ST8. After that, step ST5
, and repeats the above-mentioned operations each time a command is supplied from the host computer.

(Problem to be solved by the invention) By the way, in such a conventional PC, the PC body 1
When the data communication unit 2 finishes executing one scan, the PC main body 1WJ determines whether or not the data communication unit 2 has received a command from the host computer, and supplies data to the data communication unit 2 only when this command is received. As shown in FIG. 8(A),
When the PC main unit 1 side finishes executing one scan, the 8th
As shown in Figure (B), when the data communication unit 2 has not completed communication (command reception) with the host computer, the data communication unit 2 must hold the command until the PC main body 1 finishes executing the next one scan. First, the response generation and transmission will be delayed due to this waiting time T.

Therefore, in order to eliminate such inconvenience, each time the data communication unit 2 is supplied with a command from the host computer as shown in FIG. 9(B), the PC
PCs have already been developed that interrupt the main unit 1flll and read out the data specified by the command, for example, data A, B, and C. If mutually related data, for example each data A, B, and C, constitute a 0-digit count value, data A (or data A.

Only the digits indicated by B) are new data, which is data B.

A problem arises in that the digit indicated by C (or data C) becomes data from one scan ago.

In view of the above-mentioned circumstances, the present invention eliminates the time lag between the PC main body and the data communication unit, thereby shortening the response time of the PC side as seen from the host computer side. The purpose is to promote PCs that can be prevented from sending reliable data.

(Means for Solving the Problems) In order to solve the above problems, a PC according to the present invention includes a programmable controller main body that controls a controlled hoe machine according to a program, and a programmable controller main body that is connected to the programmable controller main body and that is connected to a host device. and a data communication unit that transmits data from the first two programmable controller main bodies to the host device in response to a data transmission request from the programmable controller, wherein the data communication unit transmits data to the programmable controller each time the programmable controller main body performs one scan. The data of the controller main body is read and stored, and when the higher-level device outputs a data transmission request, the data communication unit outputs the stored data of the programmable controller main body and supplies it to the higher-level device. It is characterized by

(Embodiment) FIG. 1 shows an embodiment of a PC according to the present invention, which is equipped with a communication unit 21, and when the PC body 20 completes one scan even when the data communication unit 221 has not received a command from the host computer. , these PC bodies 20
, if the data communication unit 21 is forcibly synchronized and data is supplied from the PC main body 20 side to the data communication unit 21 side, and the data communication unit 21 stores this data and transmits it to the host computer. When a command is supplied from the computer, it generates a response from the already stored data and sends it to the host computer.

These PC main bodies 20. The data communication unit 21 will be explained in detail. First, the PC main body 20 sequentially controls controlled devices (paths shown) according to a predetermined user program, and includes a system program memory 22, a user program memory 23, an I10 memory 24, an 110 controller 25, It is configured to include a synchronous 1/F 26 and a CPU 27.

The system program memory 22 is equipped with a non-volatile storage device such as a ROM (read-only memory) or a RAM with a backup power supply. Regulation of behavior! , lJ are stored.

Further, the user program memory 23 includes RAM, EP-ROM (replaceable ROM), and
), etc., and this user program memory 23 contains the CP
A user program for causing the tJ 27 to sequentially control the controlled 'am number is stored.

Further, the I10 memory 24 is configured with a rewritable storage device such as a RAM, and the CPLJ 2
7 uses this I10 memory 24 as a work area.

The I10 controller 25 also controls the liquid tiI III.
The CPU 27 has a plurality of input/output channel terminals connected to the I10 controller 25, and the CPU 27 takes in information (various measured values, etc.) of the controlled device via this I10 controller 25, and inputs information on the controlled W device. and send signals to control the sequence.

Further, the synchronization 1/F26 is for synchronizing the PC main body 20 side and the data communication unit 21 side, and the
27 outputs the periodic signal S1, it is taken in and supplied to the data communication unit 21 side, and when the synchronization signal S3 is supplied from the data communication unit 21, the H
Generates the ALT signal S4 to HALT the CPLI27.
state (halt state) and release the bus.

Further, the CPLJ 27 is configured with an arithmetic unit such as a microprocessor, and controls each part of the circuit according to the system program and user program.

Further, the data communication unit 21 includes the PC main body 20
It executes communication-related processing, and includes a system program memory 28, a communication controller 29, a buffer memory 30, a synchronization 1/F 31, and a CPU 32.

The system program memory 28 is equipped with a nonvolatile storage device like the system program memory 22, and stores a system program that regulates the basic operations of the CPtJ 32. .

Further, the communication controller 29 electrically connects the CPU 32 and the host computer, and receives commands (for example,
When a data transmission request, etc.) is supplied, it is taken in and supplied to the CPLI 32, and this CPU
When 32 outputs transmission data (for example, a response, etc.), it is captured and supplied to the host computer via line 33.

Further, the buffer memory 30 is configured with a rewritable storage device such as a RAM, and the buffer memory 30 is configured with a rewritable storage device such as a RAM.
J 32 uses this buffer memory 30 as a work area.

Furthermore, the synchronization 1/F31 synchronizes the data communication unit 21 side and the PC main body 20 side, and when the synchronization signal S1 is supplied from the PC main body 20 side,
An interrupt signal S2 is generated and supplied to the CPU 32, and when the CPU 32 outputs a synchronization signal S3, it is taken in and supplied to the PC main body 20 side.

In addition, CPLJ32 is an arithmetic device such as a microprocessor.
The communication processing between the PC main body 20 and the host computer is performed according to the system program stored in the system program memory 28.

Next, the operation of this PC will be described in detail with reference to the flowchart shown in FIG.

First, when the TAN is inserted into the PC, the C of the PC main body 20 is
The PU 27 executes step 5T10 of the flowchart shown in FIG. 2 according to the system program stored in the system program memory 22, and initializes each part of the circuit.

Next, the CPU 27 refreshes the I10 memory 24 in step STI 1, executes one scan of the user program in step 5T12, and imports the measurement results via the T/○ controller 25 according to the processing procedure prescribed by this user program. The necessary data, for example, data A, B, and C, are obtained by searching or sieving, and these are set in the I10 memory 24, and
The I10 controller 25 is controlled according to the processing procedure specified in the Coser program, and the I10 controller 25
Sequence control of controlled equipment connected to.

Next, the CPLI 27 executes synchronous service-like processing in step 5T13.

In this process, first a synchronization signal S1 is generated, and
Synchronize [/F26 to connect this to the data communication unit 21
The synchronous signal 1111/F31 generates an interrupt signal S2 to prevent the CPU 32 from being interrupted.

As a result, the CPLJ32 cancels the previous processing, generates the same II signal s3 in step 5T14, and sends it via the synchronization 1/F31 to the synchronization 1/F31 of the PC main body 210.
Supply to F26. As a result, the same summer/F26 is l
-I ALT signal $4 is generated to put the CPtJ 27 into a waiting state and to release the bus on the PC main body 20 side.

Next, this CPU 32 performs synchronization 1/1 in step 5T15.
110 meters on the PC main body 20 side via F31.26
4 and reads out all the data, which is then stored in the buffer memory 30.

Next, the CPtJ32 generates a synchronization release signal in step 5T16, and supplies this to the CPU 27 on the PC main body 20 side via the synchronization 1/F31.26.

After this, the CPtJ32 returns to the process before the interrupt process.

The PC main body 201111 (7) CPtJ27 operates again when the synchronization release command is supplied from the data communication unit 21 side, executes other synchronization service-like processing, and then returns to step 5T11, and returns to step 5T11 as described above. Repeat the action.

On the other hand, when this Pct, :m source is turned on, the data communication unit 21 is turned on together with the PC main body 20, and the
After U32 initializes each part of the circuit on the data communication unit 21 side, command reception processing is performed in step 5T17.

When a command such as a data transmission request is supplied from the host computer, the CPU 32 receives it via the communication controller 29, and performs processing corresponding to this command in step 5T18, for example, if the command is a data transmission request. , generates a response in a predetermined format based on the data stored in the buffer memory 30.

Next, the CPU 32 transmits this response to the host computer via the communication controller 29 in step 5T19, and then returns to step 5T17.

Then, each time a command is supplied from the host computer, the CPU 32 repeatedly executes the above-described operations.

As described above, in this embodiment, each time the PC main body 20 finishes executing one scan, data is supplied from the PC main body 20 to the data communication unit 21 and stored in advance, and this data communication unit 21 When a command is supplied from the computer, a response is generated from the stored data and this is supplied to the higher-level computer, so that commands can be supplied from the higher-level computer as shown in Figure 3 (B). Before the end, the third
As shown in Figure (A), even if the PC main body 20 has finished one step, the data corresponding to this command can be sent directly from the data communication unit 21 side to the host computer side.

Furthermore, in the embodiment described above, as shown in FIG.
The data in the I10 memory 24 provided in the main body 20 (I1
0 data) are all stored in the buffer memory 30 on the data communication unit 21 side.
), only predetermined data out of all the data in the memory 24 may be stored in the buffer memory 30.

Further, as shown in FIG. 5(B), out of all the data in the 110 memory 24, only the data specified by the read menu on the data communication unit 21 side is transferred to the buffer memory 30.
It is also possible to have it memorized.

In this case, the readout menu is created based on data supplied from the host computer, data input from a keyboard (not shown), and the like.

(Results of the Invention) As explained above, according to the present invention, it is possible to eliminate the waiting time between the PC main body and the data communication unit, thereby shortening the response time on the PC side as seen from the host computer. , it is possible to prevent uncertain data from being sent to the upper computer side.

[Brief explanation of drawings]

FIG. 1 is a circuit block diagram showing one embodiment of the present invention, and FIG.
The figure is a flowchart showing an example of the operation of the same embodiment.
A) and (B) are time charts showing operation examples of the same embodiment, FIG. 4 is a schematic diagram showing a data transfer operation of the same embodiment, and FIG. 5(A). (B) is a schematic diagram showing data transfer operations of other embodiments, FIG. 6 is a circuit block diagram showing an example of a conventional PC, FIG. 7 is a flowchart showing an example of the operation of this PC, and FIG. A) and (B) are time charts each showing an example of the operation of this PC, and FIG. 9(A). (B) is a time chart showing operation examples of other conventional P and C, respectively. 20...Programmable controller main body, 21...
・Data communication unit. Patent applicant: Tateishi Electric Co., Ltd. Agent: Patent attorney: Tetsuji Iwakura (1 other person) Figure 2

Claims (1)

[Claims] a programmable controller main body that controls a controlled device according to a program; and a data communication unit connected to the programmable controller main body that transmits data on the programmable controller main body side to the host device in response to a data transmission request from the host device. In the programmable controller, the data communication unit reads and stores data in the programmable controller main body every time the programmable controller main body performs one scan, and when the upper mine outputs a data transmission request, the data communication unit A programmable controller characterized in that data stored in the programmable controller main body is outputted and supplied to the host device.