JPS6451652A - Electronic part - Google Patents

Electronic part

Info

Publication number
JPS6451652A
JPS6451652A JP20945787A JP20945787A JPS6451652A JP S6451652 A JPS6451652 A JP S6451652A JP 20945787 A JP20945787 A JP 20945787A JP 20945787 A JP20945787 A JP 20945787A JP S6451652 A JPS6451652 A JP S6451652A
Authority
JP
Japan
Prior art keywords
substrate
nucleation surface
si3n4
shaped
onto
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20945787A
Other languages
Japanese (ja)
Inventor
Taichi Sugimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP20945787A priority Critical patent/JPS6451652A/en
Publication of JPS6451652A publication Critical patent/JPS6451652A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Landscapes

  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE:To form a circuit having an active region without using a chip by forming a nucleation surface having an area sufficiently small for crystal growth only from a single nucleus onto a substrate consisting of a non-nucleation surface and growing a crystal composed of the single nucleus to the nucleation surface. CONSTITUTION:One part of a large area substrate 1 composed of alumina is wired by a conductor 2 made up of Mo, thus manufacturing an electronic part substrate. An SiO2 film 3 is deposited onto the substrate, said substrate 1 is set into a decompression vapor growth device, an Si3N4 layer is shaped onto the SiO2 layer 3, and an Si3N4 fine region 4 as a nucleation surface is formed through patterning. Consequently, when an Si single crystal is shaped onto the substrate 1, to the surface of which a non-nucleation surface composed of SiO2 and the nucleation surface consisting of Si3N4 are formed, through a thermal CVD method, the Si single crystal 5 is shaped centering around said Si3N4 region 4. A circuit including a diode transistor and a resistor is formed centering around the single crystal 5. Accordingly, the circuit having an active region can be shaped without using a chip.
JP20945787A 1987-08-24 1987-08-24 Electronic part Pending JPS6451652A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20945787A JPS6451652A (en) 1987-08-24 1987-08-24 Electronic part

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20945787A JPS6451652A (en) 1987-08-24 1987-08-24 Electronic part

Publications (1)

Publication Number Publication Date
JPS6451652A true JPS6451652A (en) 1989-02-27

Family

ID=16573193

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20945787A Pending JPS6451652A (en) 1987-08-24 1987-08-24 Electronic part

Country Status (1)

Country Link
JP (1) JPS6451652A (en)

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