JPS6450653A - Clock phase error detection circuit - Google Patents
Clock phase error detection circuitInfo
- Publication number
- JPS6450653A JPS6450653A JP62206591A JP20659187A JPS6450653A JP S6450653 A JPS6450653 A JP S6450653A JP 62206591 A JP62206591 A JP 62206591A JP 20659187 A JP20659187 A JP 20659187A JP S6450653 A JPS6450653 A JP S6450653A
- Authority
- JP
- Japan
- Prior art keywords
- phase error
- ffs
- channels
- clock phase
- signals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
Abstract
PURPOSE:To accurately detect a clock phase error even if a carrier phase error exists by detecting a clock phase error only when zero crossing is detected simultaneously by two series of demodulation signals. CONSTITUTION:Analog signals A, B of I and Q channels are quantized into a k-bit digital signal by a clock signal C having a twice frequency fs being the modulation speed by A/D converters 11a, 11b. Signals D, E being the MSB of a k-bit quantized signal of I and Q channels are sampled and delayed by a speed fs at D.FFs 12a, 12b respectively, output signals G, H of the D.FFS 12a, 12b are sampled and delayed at a speed fs by D.FFs 22c, 22d, and given to EX.ORs 14a, 14b respectively to detect the zero crossing of I and Q channels by exclusive ORing them with the content of the D.FFs 12a, 12b. In detecting the polarity inversion (zero crossing) of both the channels, an AND circuit 15 outputs '1' and in not detecting the said inversion, the circuit 15 outputs '0' as an output signal N.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62206591A JPS6450653A (en) | 1987-08-21 | 1987-08-21 | Clock phase error detection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62206591A JPS6450653A (en) | 1987-08-21 | 1987-08-21 | Clock phase error detection circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6450653A true JPS6450653A (en) | 1989-02-27 |
| JPH0479501B2 JPH0479501B2 (en) | 1992-12-16 |
Family
ID=16525940
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62206591A Granted JPS6450653A (en) | 1987-08-21 | 1987-08-21 | Clock phase error detection circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6450653A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05110612A (en) * | 1991-10-14 | 1993-04-30 | Nippon Telegr & Teleph Corp <Ntt> | Burst signal demodulator |
| WO2000076163A1 (en) * | 1999-06-04 | 2000-12-14 | Mitsubishi Denki Kabushiki Kaisha | Phase detector, timing reproducing device comprising the same, and demodulator comprising the same |
-
1987
- 1987-08-21 JP JP62206591A patent/JPS6450653A/en active Granted
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05110612A (en) * | 1991-10-14 | 1993-04-30 | Nippon Telegr & Teleph Corp <Ntt> | Burst signal demodulator |
| WO2000076163A1 (en) * | 1999-06-04 | 2000-12-14 | Mitsubishi Denki Kabushiki Kaisha | Phase detector, timing reproducing device comprising the same, and demodulator comprising the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0479501B2 (en) | 1992-12-16 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| S533 | Written request for registration of change of name |
Free format text: JAPANESE INTERMEDIATE CODE: R313533 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| EXPY | Cancellation because of completion of term | ||
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20071216 Year of fee payment: 15 |