JPS6450420A - Alignment mark - Google Patents

Alignment mark

Info

Publication number
JPS6450420A
JPS6450420A JP62206254A JP20625487A JPS6450420A JP S6450420 A JPS6450420 A JP S6450420A JP 62206254 A JP62206254 A JP 62206254A JP 20625487 A JP20625487 A JP 20625487A JP S6450420 A JPS6450420 A JP S6450420A
Authority
JP
Japan
Prior art keywords
alignment mark
trench
groove
latent image
resist
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62206254A
Other languages
Japanese (ja)
Inventor
Yasuko Yamazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP62206254A priority Critical patent/JPS6450420A/en
Publication of JPS6450420A publication Critical patent/JPS6450420A/en
Pending legal-status Critical Current

Links

Landscapes

  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE:To eliminate application irregularities of resist and to prevent impairment in stability of resolution, by a constitution, wherein an alignment mark for a latent image is made to have a specified shape, and a part, which has been the latent image after a trench step, becomes approximately flat. CONSTITUTION:An alignment mark (a) on the side of a reticle is baked on the surface of a wafer. A trench is formed. Polycrystalline silicon is grown in the trench part. Then, a groove (c) of the trench formed by the latent image of the alignment mark (a) on the reticle side is filled with polycrystalline silicon as in the part of a groove (i) of a capacitor at an actual pattern part. The upper part of the groove as shown by an arrow (e) becomes almost flat. Even if resist (f) is applied in the next step and thereafter, application irregularities are hard to occur. Therefore, stable resolution is obtained.
JP62206254A 1987-08-21 1987-08-21 Alignment mark Pending JPS6450420A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62206254A JPS6450420A (en) 1987-08-21 1987-08-21 Alignment mark

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62206254A JPS6450420A (en) 1987-08-21 1987-08-21 Alignment mark

Publications (1)

Publication Number Publication Date
JPS6450420A true JPS6450420A (en) 1989-02-27

Family

ID=16520286

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62206254A Pending JPS6450420A (en) 1987-08-21 1987-08-21 Alignment mark

Country Status (1)

Country Link
JP (1) JPS6450420A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2359902B (en) * 1998-12-03 2002-01-30 Nec Corp Method of manufacturing a semiconductor device
US6399256B1 (en) 1998-12-03 2002-06-04 Nec Corporation Reticle having accessory pattern divided into sub-patterns
JP2010278434A (en) * 2009-05-29 2010-12-09 Asml Netherlands Bv Device and method for forming resist alignment mark through double patterning lithography process

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6610461B2 (en) 1998-03-12 2003-08-26 Nec Electronics Corporation Reticle having accessory pattern divided into sub-patterns
GB2359902B (en) * 1998-12-03 2002-01-30 Nec Corp Method of manufacturing a semiconductor device
US6399256B1 (en) 1998-12-03 2002-06-04 Nec Corporation Reticle having accessory pattern divided into sub-patterns
JP2010278434A (en) * 2009-05-29 2010-12-09 Asml Netherlands Bv Device and method for forming resist alignment mark through double patterning lithography process

Similar Documents

Publication Publication Date Title
JPS53108390A (en) Semiconductor device and its manufacture
MX173786B (en) METHOD FOR PREPARING SILICON CARBIDE SURFACES FOR GLASS GROWTH
EP0965889A3 (en) Overlay measurement technique using moire patterns
JPS6450420A (en) Alignment mark
AU2201183A (en) Self elevating formwork installation with variable geometry for making concrete surfaces, particularly very high concretesurfaces
JPS6425433A (en) Manufacture of semiconductor device
JPS6450439A (en) Manufacture of semiconductor device
TW356579B (en) Planar trenches
JPS51116051A (en) Method of correcting level difference between top edge of manhole and road surface
JPS5243370A (en) Method of forming depression in semiconductor substrate
JPS648626A (en) Dry etching of silicon using bromine gas
JPS51136289A (en) Semi-conductor producing
JPS5458365A (en) Mask aligner
JPS5595341A (en) Preparation of semiconductor device
JPS57100733A (en) Etching method for semiconductor substrate
JPS6422050A (en) Method for filling groove
JPS52130575A (en) Semiconductor device and its preparation
JPS5772346A (en) Manufacture of semiconductor device
JPS57211747A (en) Manufacture of semiconductor device
JPS5732629A (en) Mask aligner
JPS57199233A (en) Manufacture of semiconductor integrated circuit
JPS5556657A (en) Semiconductor device
JPS5312267A (en) Growth method of semiconductor crystal
JPS5314555A (en) Depositing method of impurity to silicon wafersa
JPS52127174A (en) Minute patern formation method