JPS6449322A - A/d and d/a converting circuit - Google Patents

A/d and d/a converting circuit

Info

Publication number
JPS6449322A
JPS6449322A JP20504387A JP20504387A JPS6449322A JP S6449322 A JPS6449322 A JP S6449322A JP 20504387 A JP20504387 A JP 20504387A JP 20504387 A JP20504387 A JP 20504387A JP S6449322 A JPS6449322 A JP S6449322A
Authority
JP
Japan
Prior art keywords
converting
mode
turned
output
convertor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20504387A
Other languages
Japanese (ja)
Inventor
Shinichi Wakumura
Masami Tsuchida
Hiroo Okamoto
Yoshimi Iso
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Pioneer Corp
Original Assignee
Hitachi Ltd
Pioneer Electronic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Pioneer Electronic Corp filed Critical Hitachi Ltd
Priority to JP20504387A priority Critical patent/JPS6449322A/en
Publication of JPS6449322A publication Critical patent/JPS6449322A/en
Pending legal-status Critical Current

Links

Landscapes

  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE:To widely reduce a circuit scale and to reduce power consumption by providing a shift register and a counter which can be shared respectively with an A/D convertor and a D/A convertor. CONSTITUTION:A current voltage converting circuit 104 is grounded by a non- inverted input and composed of an operational amplifier 104a in which a feedback resistance 105 is connected between an inverted input and an output. An input switch S11 is controlled by a mode signal inputted to a control input terminal 106, turned on with an A/D converting mode and turned off with a D/A converting mode. An aperture switch S16 is controlled by the mode signal inputted to a control input terminal 118, turned off with the A/D converting mode and turned on for a prescribed time so as to sample only a proper D/A converting value out of an integration output voltage with the D/A converting mode. The output of a mirror integration amplifier 110 is also supplied to a level comparator 119 with the A/D converting mode and compared with prescribed levels V1-V3 here. Thus, the circuit scale can be reduced and the power consumption can be decreased.
JP20504387A 1987-08-20 1987-08-20 A/d and d/a converting circuit Pending JPS6449322A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20504387A JPS6449322A (en) 1987-08-20 1987-08-20 A/d and d/a converting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20504387A JPS6449322A (en) 1987-08-20 1987-08-20 A/d and d/a converting circuit

Publications (1)

Publication Number Publication Date
JPS6449322A true JPS6449322A (en) 1989-02-23

Family

ID=16500502

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20504387A Pending JPS6449322A (en) 1987-08-20 1987-08-20 A/d and d/a converting circuit

Country Status (1)

Country Link
JP (1) JPS6449322A (en)

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