JPS6448396A - Timing controller for particle accelerator - Google Patents

Abstract

PURPOSE:To arrange the constitution that the setting of delay time in wide range and high resolution may be possible and it may have high accuracy and high reproducibility by providing a clock oscillator in high stability and a syn chronous circuit which takes synchronization with master pulses. CONSTITUTION:It is equipped with synchronous circuits 41, 42 which take syn chronization between output from a clock oscillator 40 provided inside and master pulses P2, plural fan out circuits 43-46 which branch these output signals into the specified number to output, and subtracting counters 47-50 connected individually to them, which are so constituted that it may control operation timing between each equipment using output from each substracting counter 47-50. That is, asynchronous jetter between the clock and the master pulses is restrained and reproducibility is improved by using synchronous circuits 41, 42. And these are made possible by using subtracting counters 47-50 to the request for wide range delay time setting and delay time circuits 26-29 limitted to the delay time width by one cycle of the clock to the request for high resolution, and it can have resolution of several n S and accuracy and reproducibility and setting width of several hundreds n S.