JPS6444724U - - Google Patents
Info
- Publication number
- JPS6444724U JPS6444724U JP13940187U JP13940187U JPS6444724U JP S6444724 U JPS6444724 U JP S6444724U JP 13940187 U JP13940187 U JP 13940187U JP 13940187 U JP13940187 U JP 13940187U JP S6444724 U JPS6444724 U JP S6444724U
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- input terminal
- inverting input
- level shift
- ratio
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Logic Circuits (AREA)
- Manipulation Of Pulses (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13940187U JPS6444724U (enExample) | 1987-09-14 | 1987-09-14 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13940187U JPS6444724U (enExample) | 1987-09-14 | 1987-09-14 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6444724U true JPS6444724U (enExample) | 1989-03-17 |
Family
ID=31402624
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13940187U Pending JPS6444724U (enExample) | 1987-09-14 | 1987-09-14 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6444724U (enExample) |
-
1987
- 1987-09-14 JP JP13940187U patent/JPS6444724U/ja active Pending