JPS6440966U - - Google Patents
Info
- Publication number
- JPS6440966U JPS6440966U JP13481987U JP13481987U JPS6440966U JP S6440966 U JPS6440966 U JP S6440966U JP 13481987 U JP13481987 U JP 13481987U JP 13481987 U JP13481987 U JP 13481987U JP S6440966 U JPS6440966 U JP S6440966U
- Authority
- JP
- Japan
- Prior art keywords
- converter
- signal
- white reference
- reference data
- video data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000003705 background correction Methods 0.000 claims description 7
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Facsimile Image Signal Circuits (AREA)
Description
第１図は本考案の一実施例のブロツク図、第２
図はＡ／Ｄ変換器の出力および本考案の一実施例
によるシエーデイング補正後のビデオデータとア
ナログビデオデータとの関係を示すグラフ、第３
図はシエーデイング補正装置が適用される画像読
取り装置の概略縦断面図、第４図は白リフアレン
スデータの一例を示すグラフ、第５図は従来のシ
エーデイング補正装置の一例を示すブロツク図、
第６図はＡ／Ｄ変換器の出力および従来のシエー
デイング補正装置によるシエーデイング補正後の
ビデオデータとアナログビデオデータとの関係を
示すグラフである。
１……Ａ／Ｄ変換器、１Ａ……基準電圧入力端
子、２……データラツチ、３……アドレスカウン
タ、４……ＲＡＭ、６……定電圧発生器、７……
Ｄ／Ａ変換器、８……セレクタ、９……バツフア
。
Fig. 1 is a block diagram of an embodiment of the present invention;
The figure is a graph showing the output of the A/D converter and the relationship between video data and analog video data after shading correction according to an embodiment of the present invention.
4 is a graph showing an example of white reference data; FIG. 5 is a block diagram showing an example of a conventional shading correction device;
FIG. 6 is a graph showing the relationship between the output of an A/D converter, video data after shading correction by a conventional shading correction device, and analog video data. 1... A/D converter, 1A... Reference voltage input terminal, 2... Data latch, 3... Address counter, 4... RAM, 6... Constant voltage generator, 7...
D/A converter, 8...Selector, 9...Buffer.
Claims (1)
ンスデータを読取り、該白リフアレンスデータに
応じて、読取られたビデオデータをシエーデイン
グ補正するシエーデイング補正装置であつて、 その基準電圧入力端子に入力される基準電圧に
応じて、白リフアレンスデータおよびビデオデー
タをデジタル信号化するＡ／Ｄ変換器と、 デジタル信号化された白リフアレンスデータを
記憶し、読取られたビデオデータのライン方向位
置に応じて、該白リフアレンスデータを出力する
ＲＡＭと、 一定となるように制御されたアナログ電圧信号
Ｖを出力する定電圧発生器と、 前記ＲＡＭより出力された白リフアレンスデー
タをアナログ信号化するＤ／Ａ変換器と、 白リフアレンスデータ読取り時には前記定電圧
発生器の出力信号を選択し、ビデオデータ読取り
時においては前記Ｄ／Ａ変換器の出力信号を選択
し、それぞれを前記Ａ／Ｄ変換器の基準電圧入力
端子に出力するセレクタとを具備し、 前記Ｄ／Ａ変換器は、デジタル信号の入力があ
つた場合に、該デジタル信号を前記Ａ／Ｄ変換器
のデジタル最大出力信号で除した値に前記アナロ
グ電圧信号Ｖを乗じた値Ｖ′のアナログ電圧信号
を出力するように構成されたことを特徴とするシ
エーデイング補正装置。[Claims for Utility Model Registration] A shading correction device that reads white reference data prior to reading video data and performs shading correction on the read video data according to the white reference data, the standard thereof. an A/D converter that converts white reference data and video data into digital signals according to a reference voltage input to a voltage input terminal; and an A/D converter that stores white reference data converted into digital signals and reads video data. a RAM that outputs the white reference data according to the position in the line direction; a constant voltage generator that outputs an analog voltage signal V that is controlled to be constant; and the white reference data output from the RAM. a D/A converter that converts the output signal into an analog signal; and selects the output signal of the constant voltage generator when reading white reference data and selects the output signal of the D/A converter when reading video data, respectively. and a selector that outputs the digital signal to a reference voltage input terminal of the A/D converter, and when a digital signal is input, the D/A converter outputs the digital signal to the reference voltage input terminal of the A/D converter. A shading correction device characterized in that it is configured to output an analog voltage signal having a value V' obtained by multiplying the value divided by the digital maximum output signal by the analog voltage signal V.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13481987U JPS6440966U (en) | 1987-09-03 | 1987-09-03 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13481987U JPS6440966U (en) | 1987-09-03 | 1987-09-03 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6440966U true JPS6440966U (en) | 1989-03-10 |
Family
ID=31393908
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13481987U Pending JPS6440966U (en) | 1987-09-03 | 1987-09-03 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6440966U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6243265A (en) * | 1985-08-20 | 1987-02-25 | Nec Corp | Shading correcting circuit |
-
1987
- 1987-09-03 JP JP13481987U patent/JPS6440966U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6243265A (en) * | 1985-08-20 | 1987-02-25 | Nec Corp | Shading correcting circuit |
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