JPS6424402U

JPS6424402U -

Info

Publication number: JPS6424402U
Application number: JP11720187U
Authority: JP
Priority date: 1987-07-30
Filing date: 1987-07-30
Publication date: 1989-02-09

Description

[Brief explanation of the drawing]

第１図はこの考案の一実施例によるアナログ入
力カードを示すブロツク図、第２図は第１図に示
したＣＰＵの処理手順を示すフローチヤート、第
３図は従来のアナログ入力カードを示すブロツク
図、第４図は第３図に示したＣＰＵの処理手順を
示すフローチヤートである。図において、３はアナログ入力カード、４_１〜
４_７は第１のアナログ入力部、５_１〜５_２はスキ
ヤナリレー、６は第２のアナログ入力部を示す。
なお、図中、同一符号は同一、または相当部分を
示す。 Fig. 1 is a block diagram showing an analog input card according to an embodiment of this invention, Fig. 2 is a flowchart showing the processing procedure of the CPU shown in Fig. 1, and Fig. 3 is a block diagram showing a conventional analog input card. 4 are flowcharts showing the processing procedure of the CPU shown in FIG. 3. In the figure, 3 is an analog input card, 4 ₁ -
4 ₇ is a first analog input section, 5 ₁ to 5 ₂ are scanner relays, and 6 is a second analog input section.
In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims

[Scope of utility model registration request]

a plurality of first analog input sections that convert a plurality of analog signals into digital signals and output the same; a scanner relay that sequentially selects the plurality of analog signals; and a scanner relay that converts the analog signal selected by the scanner relay into a digital signal and outputs the digital signal. an analog input card comprising: a second analog input section;