JPS6438882U - - Google Patents
Info
- Publication number
- JPS6438882U JPS6438882U JP1987134323U JP13432387U JPS6438882U JP S6438882 U JPS6438882 U JP S6438882U JP 1987134323 U JP1987134323 U JP 1987134323U JP 13432387 U JP13432387 U JP 13432387U JP S6438882 U JPS6438882 U JP S6438882U
- Authority
- JP
- Japan
- Prior art keywords
- distributor
- line
- input terminal
- signal input
- amplification
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000003321 amplification Effects 0.000 claims description 6
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 6
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Input Circuits Of Receivers And Coupling Of Receivers And Audio Equipment (AREA)
Description
第１図は本考案の一実施例を示す図である。第
２図は周波数特性を示す図である。第３図はＶＴ
Ｒの信号の流れを説明するための図である。
Ａ……アンテナ入力端子（アンテナ信号入力端
子）、１４……分配器、Ｂ……ＴＶ出力端子（テ
レビ用アンテナ出力端子）、３２……ブースタ回
路、ｌｂ……バイパス線路、Ｑ１……増幅用トラ
ンジスタ、ｌｇ……増幅用線路、Ｓ１……第１メ
カニカルスイツチ（メカニカルスイツチ）、ｌｖ
……電源供給線路。
FIG. 1 is a diagram showing an embodiment of the present invention. FIG. 2 is a diagram showing frequency characteristics. Figure 3 shows VT
FIG. 3 is a diagram for explaining the flow of an R signal. A...Antenna input terminal (antenna signal input terminal), 14...Distributor, B...TV output terminal (TV antenna output terminal), 32...Booster circuit, lb...Bypass line, Q1...For amplification Transistor, lg...Amplification line, S1...first mechanical switch (mechanical switch), lv
...Power supply line.
Claims (1)
入力端子Ａからの信号を２分配する分配器１４と
、この分配器１４の一方の出力が供給される内蔵
チユーナ１６と、この分配器１４の他方の出力が
供給されるテレビ用アンテナ出力端子Ｄと、前記
アンテナ信号入力端子Ａと前記分配器１４との間
に設けられ利得を選択切換可能なブースタ回路３
２とを、備えるブースタ付ビデオテープレコーダ
に於いて、 前記ブースタ回路３２は、バイパス線路ｌｂと
、増幅用トランジスタＱ１を備える増幅用線路ｌ
ｇと、前記バイパス線路ｌｂと前記増幅用線路ｌ
ｇの信号を選択的に前記分配器１４に出力するメ
カニカルスイツチＳ１と、前記増幅用トランジス
タＱ１に動作用電源を供給するべく前記メカニカ
ルスイツチＳ１の分配器側に接続された電源供給
線路ｌｖとを、 備えることを特徴とするブースタ付ビデオテー
プレコーダ。[Claims for Utility Model Registration] An antenna signal input terminal A, a distributor 14 that divides the signal from the antenna signal input terminal A into two, a built-in tuner 16 to which one output of the distributor 14 is supplied, A booster circuit 3 which is provided between the television antenna output terminal D to which the other output of the distributor 14 is supplied, the antenna signal input terminal A and the distributor 14, and is capable of selectively switching the gain.
2, the booster circuit 32 includes a bypass line lb and an amplification line l including an amplification transistor Q1.
g, the bypass line lb and the amplification line l
a mechanical switch S1 that selectively outputs the signal G to the distributor 14, and a power supply line lv connected to the distributor side of the mechanical switch S1 to supply operating power to the amplification transistor Q1. , a videotape recorder with a booster.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987134323U JPS6438882U (en) | 1987-09-02 | 1987-09-02 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987134323U JPS6438882U (en) | 1987-09-02 | 1987-09-02 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6438882U true JPS6438882U (en) | 1989-03-08 |
Family
ID=31392977
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987134323U Pending JPS6438882U (en) | 1987-09-02 | 1987-09-02 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6438882U (en) |
-
1987
- 1987-09-02 JP JP1987134323U patent/JPS6438882U/ja active Pending
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