JPS633672U - - Google Patents

Info

Publication number
JPS633672U
JPS633672U JP9496986U JP9496986U JPS633672U JP S633672 U JPS633672 U JP S633672U JP 9496986 U JP9496986 U JP 9496986U JP 9496986 U JP9496986 U JP 9496986U JP S633672 U JPS633672 U JP S633672U
Authority
JP
Japan
Prior art keywords
circuit
video
output terminal
switching
video output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9496986U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP9496986U priority Critical patent/JPS633672U/ja
Publication of JPS633672U publication Critical patent/JPS633672U/ja
Pending legal-status Critical Current

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  • Color Television Systems (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例に係るビデオ出力端
子回路と、その周辺回路の構成の概略を示したブ
ロツク図、第2図は実施例に係るビデオ出力端子
回路の具体的な回路図、第3図は実施例に係るビ
デオ出力端子回路の周波数特性図、第4図は従来
のビデオ出力端子回路と、その周辺回路の構成の
概略を示したブロツク図である。 20……ビデオ出力端子回路、21……出力増
幅回路、22……出力バツフア回路。
FIG. 1 is a block diagram schematically showing the configuration of a video output terminal circuit and its peripheral circuits according to an embodiment of the present invention, and FIG. 2 is a specific circuit diagram of the video output terminal circuit according to the embodiment. FIG. 3 is a frequency characteristic diagram of the video output terminal circuit according to the embodiment, and FIG. 4 is a block diagram schematically showing the configuration of the conventional video output terminal circuit and its peripheral circuits. 20... Video output terminal circuit, 21... Output amplifier circuit, 22... Output buffer circuit.

Claims (1)

【実用新案登録請求の範囲】 アンテナ入力端子から取り込まれた信号を復調
して得られた映像信号と、映像入力端子から取り
込まれた映像信号とを、モード切り換えスイツチ
を介して択一的に与えられ、これらを増幅して映
像出力端子へ出力する出力増幅回路を備えたビデ
オ出力端子回路であつて、 前記モード切り換えスイツチの切り換え制御信
号に基づき、前記出力増幅回路の周波数特性を切
り換える周波数特性切り換え手段を備え、この周
波数特性切り換え手段は、前記切り換え制御信号
がテレビモード選択に対応するものである場合は
高域の増幅率を上昇させるように切り換わるもの
であることを特徴とするビデオ出力端子回路。
[Claims for Utility Model Registration] A video signal obtained by demodulating a signal taken in from an antenna input terminal and a video signal taken in from a video input terminal are selectively provided via a mode changeover switch. a video output terminal circuit comprising an output amplification circuit for amplifying and outputting these signals to a video output terminal, the video output terminal circuit having a frequency characteristic switching circuit for switching the frequency characteristics of the output amplification circuit based on a switching control signal of the mode switching switch; a video output terminal, characterized in that the frequency characteristic switching means switches to increase a high frequency amplification factor when the switching control signal corresponds to television mode selection. circuit.
JP9496986U 1986-06-20 1986-06-20 Pending JPS633672U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9496986U JPS633672U (en) 1986-06-20 1986-06-20

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9496986U JPS633672U (en) 1986-06-20 1986-06-20

Publications (1)

Publication Number Publication Date
JPS633672U true JPS633672U (en) 1988-01-11

Family

ID=30958968

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9496986U Pending JPS633672U (en) 1986-06-20 1986-06-20

Country Status (1)

Country Link
JP (1) JPS633672U (en)

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