JPS6193076U - - Google Patents
Info
- Publication number
- JPS6193076U JPS6193076U JP17848984U JP17848984U JPS6193076U JP S6193076 U JPS6193076 U JP S6193076U JP 17848984 U JP17848984 U JP 17848984U JP 17848984 U JP17848984 U JP 17848984U JP S6193076 U JPS6193076 U JP S6193076U
- Authority
- JP
- Japan
- Prior art keywords
- audio
- circuit
- intermediate frequency
- frequency amplification
- amplification circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000003321 amplification Effects 0.000 claims description 4
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 5
Landscapes
- Television Receiver Circuits (AREA)
Description
第１図は、本考案の音声回路の実施例に係る音
声系を示すブロツク図、第２図は回路図、第３図
は出力信号の波形図、第４図は従来の音声系を示
すブロツク図、第５図は従来例の回路図である。
２…チユーナ、５…音声中間周波増幅回路、６
…音声多重デコーダ、９…ＦＥＴ。
Fig. 1 is a block diagram showing an audio system according to an embodiment of the audio circuit of the present invention, Fig. 2 is a circuit diagram, Fig. 3 is a waveform diagram of an output signal, and Fig. 4 is a block diagram showing a conventional audio system. FIG. 5 is a circuit diagram of a conventional example. 2... Tuner, 5... Audio intermediate frequency amplification circuit, 6
...Audio multiplex decoder, 9...FET.
Claims (1)
幅回路と、前記音声中間周波増幅回路からの信号
に対応した信号を出力する音声多重デコーダとを
備えた音声回路であつて、前記音声中間周波増幅
回路と前記音声多重デコーダとの間に、前記チユ
ーナの切り換え時に非導通状態になるように、Ｆ
ＥＴを直列に接続してある音声回路。 An audio circuit comprising an audio intermediate frequency amplification circuit that inputs a signal from a tuner, and an audio multiplex decoder that outputs a signal corresponding to the signal from the audio intermediate frequency amplification circuit, the audio intermediate frequency amplification circuit and An F is connected to the audio multiplex decoder so as to be in a non-conducting state when switching the tuner.
An audio circuit in which ETs are connected in series.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17848984U JPS6193076U (en) | 1984-11-24 | 1984-11-24 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17848984U JPS6193076U (en) | 1984-11-24 | 1984-11-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6193076U true JPS6193076U (en) | 1986-06-16 |
Family
ID=30736050
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17848984U Pending JPS6193076U (en) | 1984-11-24 | 1984-11-24 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6193076U (en) |
-
1984
- 1984-11-24 JP JP17848984U patent/JPS6193076U/ja active Pending