JPS622815Y2 - - Google Patents

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Publication number
JPS622815Y2
JPS622815Y2 JP1980176428U JP17642880U JPS622815Y2 JP S622815 Y2 JPS622815 Y2 JP S622815Y2 JP 1980176428 U JP1980176428 U JP 1980176428U JP 17642880 U JP17642880 U JP 17642880U JP S622815 Y2 JPS622815 Y2 JP S622815Y2
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JP
Japan
Prior art keywords
power supply
transistor
collector
coil
amplifier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1980176428U
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Japanese (ja)
Other versions
JPS5798018U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
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Priority to JP1980176428U priority Critical patent/JPS622815Y2/ja
Publication of JPS5798018U publication Critical patent/JPS5798018U/ja
Application granted granted Critical
Publication of JPS622815Y2 publication Critical patent/JPS622815Y2/ja
Expired legal-status Critical Current

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  • Television Receiver Circuits (AREA)
  • Amplifiers (AREA)

Description

【考案の詳細な説明】 本考案は電源供給回路に係り、直列に接続され
た複数個のトランジスタの電源電圧を直列に供給
することにより、電力消費を低減し得る電源供給
回路を提供することを目的とする。
[Detailed description of the invention] The present invention relates to a power supply circuit, and an object of the present invention is to provide a power supply circuit that can reduce power consumption by supplying the power supply voltage of a plurality of transistors connected in series in series. purpose.

第1図は本考案を適用し得る高周波信号切替装
置を有する装置の一例のブロツク系統図、第2図
は従来の電源供給回路を含む増幅器の一例の具体
的回路図を示し、両図中、同一部分には同一符号
を付してある。第1図中、受信アンテナ1により
受信されたテレビジヨン信号は高周波信号切替装
置2に供給される。高周波信号切替装置2は、既
存のテレビジヨン受像機10と磁気録画再生装置
(VTR)7とで受信アンテナ1を共用し、VTR7
の裏番組録画時はVTR内蔵の受信部(チユー
ナ、IF段)8と、テレビジヨン受像機10とへ
テレビジヨン放送信号を2分配し、またVTR7
の再生信号をモニター再生する時には、VTR内
蔵のRFコンバータ9よりテレビジヨン放送の空
チヤンネルにRF変換された再生テレビジヨン信
号をテレビジヨン受像機10のアンテナ端子へ供
給するために設けられている。
FIG. 1 shows a block system diagram of an example of a device having a high frequency signal switching device to which the present invention can be applied, and FIG. 2 shows a specific circuit diagram of an example of an amplifier including a conventional power supply circuit. Identical parts are given the same reference numerals. In FIG. 1, a television signal received by a receiving antenna 1 is supplied to a high frequency signal switching device 2. As shown in FIG. The high frequency signal switching device 2 shares the receiving antenna 1 with an existing television receiver 10 and a magnetic recording/reproducing device (VTR) 7, and
When recording a reverse program, the television broadcast signal is distributed to the VTR's built-in receiving section (tuner, IF stage) 8 and the television receiver 10, and the VTR 7
When monitoring and reproducing the reproduced signal, the RF converter 9 built in the VTR converts the reproduced television signal into an empty channel of television broadcasting, and supplies the reproduced television signal to the antenna terminal of the television receiver 10.

すなわち、受信テレビジヨン信号は分配器4に
よる損失補正のための増幅器3を通して分配器4
に供給され、ここで2分配されて一方はVTR7
の受信部8に、他方は合成回路6による混合損失
分の高周波増幅と高周波信号切替装置2の出力段
から入力段に戻る信号に対するアイソレーシヨン
対策のために設けられている増幅器5を経て合成
回路6に供給される。合成回路6は増幅器5より
の受信テレビジヨン信号とRFコンバータ9より
の空チヤンネルにRF変換されたVTR再生テレビ
ジヨン信号とを夫々混合合成し、その合成テレビ
ジヨン信号を同時にテレビジヨン受像機10のア
ンテナ端子に供給する。
That is, the received television signal is transmitted through the amplifier 3 for loss correction by the distributor 4.
is supplied to the VTR7, where it is distributed into two parts, and one is supplied to the VTR7.
The other one is synthesized via an amplifier 5 provided for high frequency amplification for the mixing loss by a combining circuit 6 and isolation measures for the signal returned from the output stage to the input stage of the high frequency signal switching device 2. It is supplied to circuit 6. The synthesis circuit 6 mixes and synthesizes the received television signal from the amplifier 5 and the VTR reproduced television signal which has been RF converted into an empty channel from the RF converter 9, and simultaneously sends the synthesized television signal to the television receiver 10. Supplied to the antenna terminal.

これにより、VTR再生時はスイツチ操作を行
なう必要なくテレビジヨン受像機10により空チ
ヤンネルでモニター再生することができる。
As a result, during VTR playback, it is possible to monitor playback using an empty channel on the television receiver 10 without having to operate a switch.

上記の増幅器5は第2図に示す如く、受信テレ
ビジヨン信号入力端子11、電源端子12を有し
ており、所定のアイソレーシヨンを得るために
NPNトランジスタQ1,Q2が2段直列に接続され
た構成とされている。
As shown in FIG. 2, the above amplifier 5 has a received television signal input terminal 11 and a power supply terminal 12.
It has a configuration in which two stages of NPN transistors Q 1 and Q 2 are connected in series.

しかるに、従来は増幅器5を構成するトランジ
スタQ1,Q2の電源電圧は、コイルL1,L2を介し
て端子12よりの電源電圧+Bが夫々トランジス
タQ1,Q2のコレクタに並列に印加されていたた
め、例えばトランジスタQ1,Q2の各コレクタ電
流が34mA流れるよう構成した場合は、少なくと
も端子12においては68mA以上の電流を流す必
要があり、消費電力を要するという欠点があつ
た。
However, conventionally, the power supply voltage of the transistors Q 1 and Q 2 constituting the amplifier 5 is such that the power supply voltage +B from the terminal 12 is applied in parallel to the collectors of the transistors Q 1 and Q 2, respectively, via the coils L 1 and L 2 . Therefore, if the transistors Q 1 and Q 2 were configured to have a collector current of 34 mA, for example, a current of 68 mA or more would have to flow at least at the terminal 12, resulting in a disadvantage of high power consumption.

本考案は上記の欠点を除去するものであり、第
2図乃至第5図と共にその各実施例につき説明す
る。
The present invention eliminates the above-mentioned drawbacks, and its embodiments will be described in conjunction with FIGS. 2 to 5.

第3図は本考案になる電源供給回路の第1実施
例が適用された増幅器の具体的回路図を示す。同
図中、第2図と同一構成部分には同一符号を付
し、その説明を省略する。本実施例では第1の電
源端子12は第1のコイルであるコイルL2を介
してトランジスタQ2のコレクタに接続され、ト
ランジスタQ2のエミツタと第2の電源端子GND
との間にエミツタ抵抗及びバイパスコンデンサ
C1が直列に接続され、コンデンサC1とエミツタ
抵抗との接続点が、高周波バイパスを完全にす
るための交流除去用フイルタを構成するコイル
L3及びコンデンサC2と第2のコイルであるコイ
ルL1とを夫々直列に介してトランジスタQ1のコ
レクタに接続されている。これらは増幅器5′を
構成している。
FIG. 3 shows a specific circuit diagram of an amplifier to which the first embodiment of the power supply circuit according to the present invention is applied. In the figure, the same components as those in FIG. 2 are denoted by the same reference numerals, and the explanation thereof will be omitted. In this embodiment, the first power supply terminal 12 is connected to the collector of the transistor Q2 via the first coil L2 , and the emitter of the transistor Q2 and the second power supply terminal GND are connected to each other.
An emitter resistor and bypass capacitor between
C 1 is connected in series, and the connection point between capacitor C 1 and emitter resistor constitutes an AC removal filter to complete high frequency bypass.
It is connected to the collector of the transistor Q 1 via the coil L 3 and the capacitor C 2 and the coil L 1 which is the second coil, respectively. These constitute an amplifier 5'.

これにより、第1の電源端子12より例えば
12Vの電源電圧が印加された場合は、上記点の
電圧を6Vとすることができる。すなわち、トラ
ンジスタQ1,Q2は夫々電源電圧12Vの半分の6V
ずつ電源電圧として印加される。従つて、トラン
ジスタQ1,Q2の各コレクタ電流は必要な34mAが
得られ、しかも電源端子12には34mA程度の電
流を流すだけでよく従来に比し消費電力を低減す
ることができる。
As a result, for example, from the first power supply terminal 12
If a power supply voltage of 12V is applied, the voltage at the above point can be 6V. In other words, transistors Q 1 and Q 2 each have a power supply voltage of 6V, which is half of the power supply voltage of 12V.
is applied as the power supply voltage. Therefore, the necessary collector current of 34 mA can be obtained for each of the transistors Q 1 and Q 2 , and only about 34 mA of current needs to be passed through the power supply terminal 12 , making it possible to reduce power consumption compared to the conventional case.

次に本考案回路の第2実施例につき説明する
に、第4図は本考案回路の第2実施例が適用され
た増幅器の具体的回路図を示す。同図中、第3図
と同一構成部分には同一符号を付し、その説明を
省略する。第4図において、2段直列に接続され
たトランジスタQ1,Q2その他により増幅器5″が
構成されている。本実施例では、点は第2のコ
イルであるコイルL4を介してトランジスタQ1
接続されている。このコイルL4はバランコイル
で構成されているが、これにより空芯コイルを使
用した場合の帯域特性(第5図に実線で示す)に
比し、特に低域の帯域特性を向上することができ
る。第5図中、破線はバランコイルの帯域特性を
示す。
Next, a second embodiment of the circuit of the present invention will be described. FIG. 4 shows a specific circuit diagram of an amplifier to which the second embodiment of the circuit of the present invention is applied. In the figure, the same components as those in FIG. 3 are designated by the same reference numerals, and their explanations will be omitted. In FIG. 4, an amplifier 5'' is composed of transistors Q 1 , Q 2 and others connected in series in two stages. In this embodiment, the point is the transistor Q via the second coil L 4 1. This coil L 4 is composed of a balun coil, which has a particularly low frequency band characteristic (shown by the solid line in Figure 5) compared to when an air-core coil is used. The band characteristics can be improved. In FIG. 5, the broken line indicates the band characteristics of the balun coil.

また本実施例は、Q1,Q2段の高周波増幅利得
が10dB以下と利得が低いため第1実施例のコイ
ルL3及びコンデンサC1,C2によるπ形の交流除
去フイルタを用いなくとも、コンデンサC1のみ
で十分なバイパス効果が得られ、よつて電源端子
12の電源電圧の半分の電圧を電源電圧としてト
ランジスタQ1のコレクタに印加することができ
る点に鑑みなされたもので、第1実施例に比し部
品点数を削減できる。
In addition, in this embodiment, the high frequency amplification gain of the two stages Q 1 and Q is low, 10 dB or less, so it is possible to eliminate the need for the π-type AC removal filter using the coil L 3 and capacitors C 1 and C 2 of the first embodiment. This was done in view of the fact that a sufficient bypass effect can be obtained with only the capacitor C 1 , and thus half the voltage of the power supply voltage of the power supply terminal 12 can be applied to the collector of the transistor Q 1 as the power supply voltage. The number of parts can be reduced compared to the first embodiment.

本実施例の場合も、トランジスタQ2のコレク
タと点との間の電位差及びトランジスタQ1
コレクタと第2の電源端子(ここではGND)と
の間の電位差を夫々第1の電源端子12の電源電
圧の略1/2にすることができるので、従来に比し
電力消費を低減できる。
In the case of this embodiment as well, the potential difference between the collector of the transistor Q 2 and the point and the potential difference between the collector of the transistor Q 1 and the second power supply terminal (GND in this case) are respectively set to the first power supply terminal 12. Since the power supply voltage can be reduced to approximately 1/2, power consumption can be reduced compared to conventional methods.

上述の如く、本考案になる電源供給回路は、増
幅器の後段の第2のトランジスタのコレクタに第
1のコイルを介して接続された第1の電源端子
と、増幅器の前段の第1のトランジスタのエミツ
タが抵抗を介して接続された第2の電源端子と、
第2のトランジスタのエミツタ抵抗と第2の電源
端子との間に接続されたバイパスコンデンサと、
バイパスコンデンサ及びエミツタ抵抗の接続点と
第1のトランジスタのコレクタとを接続する第2
のコイルとより構成したため、第1及び第2の電
源端子間の電位差の1/2の電源電圧を第1,第2
夫々のトランジスタに印加することができ、従つ
て第1の電源端子を第1,第2のトランジスタの
コレクタに夫々各別に接続する従来の電源供給回
路に比し電力消費を低減することができ、また、
第2のコイルは第1の電源端子より第2のトラン
ジスタに印加された電源電圧を無駄に降下させる
ことなく第1のトランジスタに印加すると共に、
第1のトランジスタの出力信号を阻止して第2の
トランジスタのエミツタに到達させず第1及び第
2のトランジスタ間の干渉を防止し、更に第1の
トランジスタの負荷としても機能しており、部品
点数最小にして所期の効果を得ることができ、ま
た上記第2のコイルとしてバランコイルを使用し
た場合は空芯コイルを用いた場合に比し帯域特性
を向上することができる等の特長を有するもので
ある。
As described above, the power supply circuit according to the present invention has a first power supply terminal connected to the collector of the second transistor in the rear stage of the amplifier via the first coil, and a first power supply terminal connected to the collector of the second transistor in the rear stage of the amplifier. a second power supply terminal to which the emitter is connected via a resistor;
a bypass capacitor connected between the emitter resistance of the second transistor and the second power supply terminal;
A second transistor connects the connection point of the bypass capacitor and the emitter resistor to the collector of the first transistor.
Since the power supply voltage is 1/2 of the potential difference between the first and second power supply terminals,
can be applied to each transistor, and therefore, power consumption can be reduced compared to a conventional power supply circuit in which the first power supply terminal is connected to the collectors of the first and second transistors, respectively. Also,
The second coil applies the power supply voltage applied to the second transistor from the first power supply terminal to the first transistor without unnecessary drop, and
It blocks the output signal of the first transistor from reaching the emitter of the second transistor to prevent interference between the first and second transistors, and also functions as a load for the first transistor. The desired effect can be obtained by minimizing the number of points, and when a balun coil is used as the second coil, the band characteristics can be improved compared to when an air-core coil is used. It is something that you have.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案を適用し得る高周波信号切替装
置を有する装置の一例を示すブロツク系統図、第
2図は従来の電源供給回路を含む増幅器の一例を
示す具体的回路図、第3図及び第4図は夫々本考
案回路の第1及び第2実施例を含む増幅器を示す
具体的回路図、第5図は第4図の動作説明用特性
図である。 2……高周波信号切替装置、3,5,5′,
5″……増幅器、7……磁気録画再生装置
(VTR)、11……受信テレビジヨン信号入力端
子、12……第1の電源端子、GND……第2の
電源端子、L1〜L4……コイル、Q1,Q2……増幅
用NPNトランジスタ、C1……バイパスコンデン
サ。
Fig. 1 is a block system diagram showing an example of a device having a high frequency signal switching device to which the present invention can be applied, Fig. 2 is a specific circuit diagram showing an example of an amplifier including a conventional power supply circuit, and Figs. FIG. 4 is a specific circuit diagram showing an amplifier including the first and second embodiments of the circuit of the present invention, and FIG. 5 is a characteristic diagram for explaining the operation of FIG. 4. 2...High frequency signal switching device, 3, 5, 5',
5''...Amplifier, 7...Magnetic recording and reproducing device (VTR), 11...Received television signal input terminal, 12...First power terminal, GND...Second power terminal, L 1 to L 4 ... Coil, Q 1 , Q 2 ... NPN transistor for amplification, C 1 ... Bypass capacitor.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 入来する信号をベースに供給されて増幅しコレ
クタより出力する第1のトランジスタと、該第1
のトランジスタのコレクタよりの信号をベースに
供給されて増幅しコレクタより出力する第2のト
ランジスタとよりなる増幅器に電源電圧を供給す
る回路において、該増幅器の後段の該第2のトラ
ンジスタのコレクタに第1のコイルを介して接続
された第1の電源端子と、該増幅器の前段の該第
1のトランジスタのエミツタが抵抗を介して接続
された第2の電源端子と、該第2のトランジスタ
のエミツタ抵抗と該第2の電源端子との間に接続
されたバイパスコンデンサと、該バイパスコンデ
ンサ及びエミツタ抵抗の接続点と該第1のトラン
ジスタのコレクタとを接続する第2のコイルとよ
り構成した電源供給回路。
a first transistor that is supplied with an incoming signal to its base, amplifies it, and outputs it from its collector;
In a circuit for supplying a power supply voltage to an amplifier comprising a second transistor which receives a signal from the collector of the transistor at its base, amplifies the signal, and outputs it from the collector, a first power supply terminal connected via a coil, a second power supply terminal connected to an emitter of the first transistor in the front stage of the amplifier via a resistor, and an emitter of the second transistor. A power supply comprising a bypass capacitor connected between a resistor and the second power supply terminal, and a second coil connecting a connection point between the bypass capacitor and the emitter resistor and the collector of the first transistor. circuit.
JP1980176428U 1980-12-09 1980-12-09 Expired JPS622815Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1980176428U JPS622815Y2 (en) 1980-12-09 1980-12-09

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1980176428U JPS622815Y2 (en) 1980-12-09 1980-12-09

Publications (2)

Publication Number Publication Date
JPS5798018U JPS5798018U (en) 1982-06-16
JPS622815Y2 true JPS622815Y2 (en) 1987-01-22

Family

ID=29969414

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1980176428U Expired JPS622815Y2 (en) 1980-12-09 1980-12-09

Country Status (1)

Country Link
JP (1) JPS622815Y2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0753296Y2 (en) * 1986-04-02 1995-12-06 アルパイン株式会社 Audio playback equipment
JP2682415B2 (en) * 1993-12-22 1997-11-26 日本電気株式会社 Semiconductor integrated circuit
JP5655526B2 (en) * 2010-11-29 2015-01-21 住友電気工業株式会社 Electronic circuit
JP5820176B2 (en) * 2011-07-21 2015-11-24 住友電気工業株式会社 Electronic circuit

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53889A (en) * 1976-06-24 1978-01-07 Mitsubishi Electric Corp Jointing method of conductor
JPS5760709A (en) * 1980-09-27 1982-04-12 Maspro Denkoh Corp Bias system for amplifying circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53889A (en) * 1976-06-24 1978-01-07 Mitsubishi Electric Corp Jointing method of conductor
JPS5760709A (en) * 1980-09-27 1982-04-12 Maspro Denkoh Corp Bias system for amplifying circuit

Also Published As

Publication number Publication date
JPS5798018U (en) 1982-06-16

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