JPS6438029U - - Google Patents

Info

Publication number
JPS6438029U
JPS6438029U JP13079587U JP13079587U JPS6438029U JP S6438029 U JPS6438029 U JP S6438029U JP 13079587 U JP13079587 U JP 13079587U JP 13079587 U JP13079587 U JP 13079587U JP S6438029 U JPS6438029 U JP S6438029U
Authority
JP
Japan
Prior art keywords
storage device
input
encoding
decoding circuit
external storage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13079587U
Other languages
Japanese (ja)
Other versions
JP2524129Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987130795U priority Critical patent/JP2524129Y2/en
Publication of JPS6438029U publication Critical patent/JPS6438029U/ja
Application granted granted Critical
Publication of JP2524129Y2 publication Critical patent/JP2524129Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Image Processing (AREA)
  • Analogue/Digital Conversion (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図および第２図は本考案の第１および第２
の実施例を示すブロツク図、第３図および第４図
は従来の符号復号化回路の入出力装置を示すブロ
ツク図。 符号の説明、１……符号復号化回路、２……内
部記憶装置、３……外部記憶装置、４，５……ダ
イレクトメモリアクセスコントローラ、６，７…
…バス、８……ＳＣＳＩインターフエース、９…
…データ処理部、１０……入力部、１１……ＣＰ
Ｕ、１２……ＲＯＭ、１３……プリンタ、１４…
…表示部、１５……画像読取部、１６……ＭＯＤ
ＥＭ、１７……ＮＣＵ。 Figures 1 and 2 are the first and second figures of the present invention.
FIGS. 3 and 4 are block diagrams showing an input/output device of a conventional code/decoder circuit. Explanation of symbols, 1... Code decoding circuit, 2... Internal storage device, 3... External storage device, 4, 5... Direct memory access controller, 6, 7...
…bus, 8…SCSI interface, 9…
...Data processing section, 10...Input section, 11...CP
U, 12...ROM, 13...Printer, 14...
...display section, 15...image reading section, 16...MOD
EM, 17...NCU.

Claims (1)

【実用新案登録請求の範囲】 内部記憶装置および外部記憶装置のデータを符
号化および復号化する符号復号化回路と、 前記外部記憶装置を前記符号復号化回路へ直接
接続する第１の入出力経路と、 前記外部記憶装置を前記内部記憶装置を介して
前記符号復号化回路へ接続する第２の入出力経路
と、 前記第１あるいは第２の入出力経路の選択に基
いて前記外部記憶装置と前記符号復号化回路の間
のデータの転送経路を制御する入出力経路選択手
段を有することを特徴とする符号復号化回路の入
出力装置。[Claims for Utility Model Registration] An encoding/decoding circuit that encodes and decodes data in an internal storage device and an external storage device; and a first input/output path that directly connects the external storage device to the encoding/decoding circuit. a second input/output path connecting the external storage device to the encoding/decoding circuit via the internal storage device; An input/output device for a code/decoder circuit, comprising input/output route selection means for controlling a data transfer route between the code/decoder circuits.
JP1987130795U 1987-08-27 1987-08-27 Input / output device of code decoding circuit Expired - Lifetime JP2524129Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987130795U JP2524129Y2 (en) 1987-08-27 1987-08-27 Input / output device of code decoding circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987130795U JP2524129Y2 (en) 1987-08-27 1987-08-27 Input / output device of code decoding circuit

Publications (2)

Publication Number Publication Date
JPS6438029U true JPS6438029U (en) 1989-03-07
JP2524129Y2 JP2524129Y2 (en) 1997-01-29

Family

ID=31386283

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987130795U Expired - Lifetime JP2524129Y2 (en) 1987-08-27 1987-08-27 Input / output device of code decoding circuit

Country Status (1)

Country Link
JP (1) JP2524129Y2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0677954A (en) * 1990-06-29 1994-03-18 Digital Equip Corp <Dec> Apparatus and method for processing of code provided with arbitrary selective status encoding

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5433641A (en) * 1977-08-22 1979-03-12 Toshiba Corp Information processor
JPS6076447U (en) * 1983-10-29 1985-05-28 神鋼電機株式会社 Programmable high-speed/low-speed mode switching bus
JPS6289042U (en) * 1985-11-22 1987-06-06

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5433641A (en) * 1977-08-22 1979-03-12 Toshiba Corp Information processor
JPS6076447U (en) * 1983-10-29 1985-05-28 神鋼電機株式会社 Programmable high-speed/low-speed mode switching bus
JPS6289042U (en) * 1985-11-22 1987-06-06

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0677954A (en) * 1990-06-29 1994-03-18 Digital Equip Corp <Dec> Apparatus and method for processing of code provided with arbitrary selective status encoding

Also Published As

Publication number Publication date
JP2524129Y2 (en) 1997-01-29

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