JPS6437643A - Peripheral control system - Google Patents

Peripheral control system

Info

Publication number
JPS6437643A
JPS6437643A JP62194781A JP19478187A JPS6437643A JP S6437643 A JPS6437643 A JP S6437643A JP 62194781 A JP62194781 A JP 62194781A JP 19478187 A JP19478187 A JP 19478187A JP S6437643 A JPS6437643 A JP S6437643A
Authority
JP
Japan
Prior art keywords
cpu
peripheral control
interface
control system
interfaces
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62194781A
Other languages
Japanese (ja)
Inventor
Kazuo Takagaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62194781A priority Critical patent/JPS6437643A/en
Publication of JPS6437643A publication Critical patent/JPS6437643A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)

Abstract

PURPOSE:To constitute an I/O control system with high general usefulness by providing the titled system with plural I/O interfaces for connecting between a central processing unit (CPU) and a peripheral control device. CONSTITUTION:The peripheral control device 1 is connected to the CPU 2 through the I/O interfaces 10, 11 having the same function. When a certain I/O operation executed by the device 1 from the CPU 2 through the I/O interface 10 is disabled on the way of the operation, the device 1 stores the interruption of said I/O operation on the I/O interface 10 and informs the contents to the CPU 2 through the I/O interface 11.
JP62194781A 1987-08-04 1987-08-04 Peripheral control system Pending JPS6437643A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62194781A JPS6437643A (en) 1987-08-04 1987-08-04 Peripheral control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62194781A JPS6437643A (en) 1987-08-04 1987-08-04 Peripheral control system

Publications (1)

Publication Number Publication Date
JPS6437643A true JPS6437643A (en) 1989-02-08

Family

ID=16330149

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62194781A Pending JPS6437643A (en) 1987-08-04 1987-08-04 Peripheral control system

Country Status (1)

Country Link
JP (1) JPS6437643A (en)

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