JPS643747A - Software logical device - Google Patents

Software logical device

Info

Publication number
JPS643747A
JPS643747A JP62157693A JP15769387A JPS643747A JP S643747 A JPS643747 A JP S643747A JP 62157693 A JP62157693 A JP 62157693A JP 15769387 A JP15769387 A JP 15769387A JP S643747 A JPS643747 A JP S643747A
Authority
JP
Japan
Prior art keywords
arithmetic
program
basic
logical
reading
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62157693A
Other languages
Japanese (ja)
Other versions
JPH0762831B2 (en
Inventor
Satoru Suzuki
Yukio Nagaoka
Shigeru Izumi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP62157693A priority Critical patent/JPH0762831B2/en
Publication of JPS643747A publication Critical patent/JPS643747A/en
Publication of JPH0762831B2 publication Critical patent/JPH0762831B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Tests Of Electronic Circuits (AREA)
  • Testing And Monitoring For Control Systems (AREA)
  • Debugging And Monitoring (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Programmable Controllers (AREA)

Abstract

PURPOSE:To ensure the satisfactory perfectness of a logical device and also to confirm the working of the logical device in a low frequency, by describing a logical arithmetic program with use of the basic logical arithmetic elements of AND, OR, etc., and reading the arithmetic values of output variables of those elements out of an external device. CONSTITUTION:A test pattern production means 21 produces a test pattern to check whether a program 140 stored in a program memory means 14 is correct or not. Then the means 21 outputs the test pattern to a signal input means 11. At the same time, the expected value of the output variable of a basic arithmetic element is also obtained at that time point. A test result reading means 22 reads the arithmetic value of a basic arithmetic element output memory means 15 of a software logical device 1. A variable address information reading means 23 reads the memory contents of an address memory means 16 of the device 1 and stores them into a reading variable address memory means 24. A comparison means 25 compares the arithmetic value of the output variable of the basic arithmetic element read out by the means 22 with the expected value of the output variable of the basic arithmetic element produced by the means 21. Thus the soundness of the program 140 stored in the means 14 of the device 1 is checked and this checking result is outputted via an interface 26.
JP62157693A 1987-06-26 1987-06-26 Software logic unit Expired - Lifetime JPH0762831B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62157693A JPH0762831B2 (en) 1987-06-26 1987-06-26 Software logic unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62157693A JPH0762831B2 (en) 1987-06-26 1987-06-26 Software logic unit

Publications (2)

Publication Number Publication Date
JPS643747A true JPS643747A (en) 1989-01-09
JPH0762831B2 JPH0762831B2 (en) 1995-07-05

Family

ID=15655320

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62157693A Expired - Lifetime JPH0762831B2 (en) 1987-06-26 1987-06-26 Software logic unit

Country Status (1)

Country Link
JP (1) JPH0762831B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7942413B2 (en) 2007-11-14 2011-05-17 Konica Minolta Business Technologies, Inc. Image forming apparatus provided with output tray and control method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7942413B2 (en) 2007-11-14 2011-05-17 Konica Minolta Business Technologies, Inc. Image forming apparatus provided with output tray and control method thereof

Also Published As

Publication number Publication date
JPH0762831B2 (en) 1995-07-05

Similar Documents

Publication Publication Date Title
US5051997A (en) Semiconductor integrated circuit with self-test function
KR870003430A (en) Semiconductor integrated circuit device
JPS6483169A (en) Integrated circuit device
EP0356999A3 (en) Memory tester
JPS5585265A (en) Function test evaluation device for integrated circuit
KR920000021A (en) Numerical Control Device
JPS643747A (en) Software logical device
MY105219A (en) Signal processing apparatus and method
KR930018426A (en) Curing Screening Device
JPS55131810A (en) Programmable sequencer
DE3277598D1 (en) Scan-out circuitry
JPS6462736A (en) Error detecting circuit
JPS6428747A (en) Microprocessor
JPS55166757A (en) Check unit for overlapping use of output instruction
JPS5532110A (en) Check circuit for error correcting circuit
SU1524713A1 (en) DEVICE FOR THE CONTROL OF PARAMETERS
KR930016883A (en) Electronics
JPS5717063A (en) Test circuit of microcomputer
SU1644091A1 (en) Time programming device
JPS55141679A (en) Ic tester
JPS6470848A (en) Picture display control system
PETERS A mixed H 2/H (infinity) function for a discrete time system
JPS6484341A (en) In-circuit emulator
JPS5729146A (en) Logical circuit including memory array
LANGBERG et al. Transformation yielding reliability models based on independent random variables: A survey[Interim Report]