JPS6437147A - Trouble supervisory system - Google Patents

Trouble supervisory system

Info

Publication number
JPS6437147A
JPS6437147A JP19325487A JP19325487A JPS6437147A JP S6437147 A JPS6437147 A JP S6437147A JP 19325487 A JP19325487 A JP 19325487A JP 19325487 A JP19325487 A JP 19325487A JP S6437147 A JPS6437147 A JP S6437147A
Authority
JP
Japan
Prior art keywords
circuit
supervisory
supervised
trouble
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19325487A
Other languages
Japanese (ja)
Inventor
Yoshitaka Kato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP19325487A priority Critical patent/JPS6437147A/en
Publication of JPS6437147A publication Critical patent/JPS6437147A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To easily locate trouble by providing a supervisory circuit between circuits to be monitored and generating a prescribed monitor pattern. CONSTITUTION:The prescribed supervisory pattern which a pattern generator 1 generates is inserted to a monitor time slot in the signal, which is inputted from a circuit to be supervised in the preceding stage through a signal bus l1, by an inserting circuit 2 and is given to a circuit to be supervised in the succeeding stage through a signal bus l2. A supervisory pattern in the supervisory time slot of the signal which is branched from the signal bus l and is inputted from the circuit to be supervised in the preceding stage is compared with the prescribed supervisory pattern by a comparing circuit 3, and an alarm is outputted from an alarm output terminal 4 if this comparison does not result in coincidence. Since only the supervisory circuit in the succeeding stage of the circuit to be supervised tored generates the alarm when trouble occurs in this circuit to be supervised trouble is easily located, and even double trouble can be located.
JP19325487A 1987-07-31 1987-07-31 Trouble supervisory system Pending JPS6437147A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19325487A JPS6437147A (en) 1987-07-31 1987-07-31 Trouble supervisory system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19325487A JPS6437147A (en) 1987-07-31 1987-07-31 Trouble supervisory system

Publications (1)

Publication Number Publication Date
JPS6437147A true JPS6437147A (en) 1989-02-07

Family

ID=16304896

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19325487A Pending JPS6437147A (en) 1987-07-31 1987-07-31 Trouble supervisory system

Country Status (1)

Country Link
JP (1) JPS6437147A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0715778A (en) * 1993-06-25 1995-01-17 Nec Corp Time division synchronous multiplex bus circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0715778A (en) * 1993-06-25 1995-01-17 Nec Corp Time division synchronous multiplex bus circuit

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