JPS643578A - Test circuit for semiconductor integrated circuit - Google Patents

Test circuit for semiconductor integrated circuit

Info

Publication number
JPS643578A
JPS643578A JP62160590A JP16059087A JPS643578A JP S643578 A JPS643578 A JP S643578A JP 62160590 A JP62160590 A JP 62160590A JP 16059087 A JP16059087 A JP 16059087A JP S643578 A JPS643578 A JP S643578A
Authority
JP
Japan
Prior art keywords
address
circuit
test
rom
generating circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62160590A
Other languages
Japanese (ja)
Other versions
JP2604378B2 (en
Inventor
Nobuhito Morikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC IC Microcomputer Systems Co Ltd
Original Assignee
NEC IC Microcomputer Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC IC Microcomputer Systems Co Ltd filed Critical NEC IC Microcomputer Systems Co Ltd
Priority to JP62160590A priority Critical patent/JP2604378B2/en
Publication of JPS643578A publication Critical patent/JPS643578A/en
Application granted granted Critical
Publication of JP2604378B2 publication Critical patent/JP2604378B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Tests Of Electronic Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PURPOSE:To obtain a high effect with an inexpensive equipment by providing an address generating circuit which generates the address of a mu-ROM and a final address generating circuit which detects the final address of the above- mentioned address and generates a reset signal. CONSTITUTION:A test mode detecting circuit 17 detects a test input signal (a) and outputs a test signal (b) when said input signal is inputted thereto. The final address detecting circuit 14, an address incrementing circuit 13 and an external output prohibiting circuit 16 are enabled by this test signal (b). However, an address modification control circuit 15 is disabled. The address supply to the mu-ROM 10 in an ordinary operation is determined by determining a mu-ROM address buss 11 by the circuit 15 and feeding the address from the circuit 13 to the address generating circuit 12. The addresses added with 1 by the address incrementing circuit 13 are thereafter outputted successively from the address generating circuit 12.
JP62160590A 1987-06-26 1987-06-26 Test circuit for semiconductor integrated circuit Expired - Lifetime JP2604378B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62160590A JP2604378B2 (en) 1987-06-26 1987-06-26 Test circuit for semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62160590A JP2604378B2 (en) 1987-06-26 1987-06-26 Test circuit for semiconductor integrated circuit

Publications (2)

Publication Number Publication Date
JPS643578A true JPS643578A (en) 1989-01-09
JP2604378B2 JP2604378B2 (en) 1997-04-30

Family

ID=15718243

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62160590A Expired - Lifetime JP2604378B2 (en) 1987-06-26 1987-06-26 Test circuit for semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JP2604378B2 (en)

Also Published As

Publication number Publication date
JP2604378B2 (en) 1997-04-30

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