JPS6433614A - Memory selection control system - Google Patents
Memory selection control systemInfo
- Publication number
- JPS6433614A JPS6433614A JP62191382A JP19138287A JPS6433614A JP S6433614 A JPS6433614 A JP S6433614A JP 62191382 A JP62191382 A JP 62191382A JP 19138287 A JP19138287 A JP 19138287A JP S6433614 A JPS6433614 A JP S6433614A
- Authority
- JP
- Japan
- Prior art keywords
- memory
- memories
- contents
- input address
- signal output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
PURPOSE:To clear and copy memories at a high speed by setting optionally the contents a memory selecting state diagram and changing freely the selection of memories to an input address. CONSTITUTION:A memory selection control part 20 consists of an address converting part 30, a memory selecting part 40 and a memory selecting state table part 50. The part 50 stores the relationship between an input address and a memory selection signal output in the form of a memory selecting state diagram. Then the part 30 converts the input address into the corresponding memory selection signal output according to the contents of said state diagram. The part 40 selects the memory pointed by the memory selection signal output converted by the part 30. Thus the selection of memories 10-17 can be freely changed as necessary to the input address. As a result, the time needed for clearing the contents of all memories can be extremely shortened together with the time needed for copying the memory contents to plural memories for each memory.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62191382A JPS6433614A (en) | 1987-07-29 | 1987-07-29 | Memory selection control system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62191382A JPS6433614A (en) | 1987-07-29 | 1987-07-29 | Memory selection control system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6433614A true JPS6433614A (en) | 1989-02-03 |
Family
ID=16273664
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62191382A Pending JPS6433614A (en) | 1987-07-29 | 1987-07-29 | Memory selection control system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6433614A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007171065A (en) * | 2005-12-26 | 2007-07-05 | National Institute Of Advanced Industrial & Technology | Wideband frequency characteristic measuring device |
US11663255B2 (en) | 2019-05-23 | 2023-05-30 | International Business Machines Corporation | Automatic collaboration between distinct responsive devices |
-
1987
- 1987-07-29 JP JP62191382A patent/JPS6433614A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007171065A (en) * | 2005-12-26 | 2007-07-05 | National Institute Of Advanced Industrial & Technology | Wideband frequency characteristic measuring device |
US11663255B2 (en) | 2019-05-23 | 2023-05-30 | International Business Machines Corporation | Automatic collaboration between distinct responsive devices |
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