JPS6432365A - Data transfer system - Google Patents

Abstract

PURPOSE:To improve the data transfer efficiency of a bus by securing such a constitution where a DMA controller sends both main and secondary instructions to the bus within the same bus cycle for execution of both instructions after the addresses are set at the address holding devices of memories respectively. CONSTITUTION:A DMA controller 30 or a processor 1 sets the addresses at the address holding devices 34 of memories 32 and 33 before the transfer of data is started. Thus both devices 34 hold those set addresses and the controller 30 starts the control of the data transfer with the instruction of the processor 1. Then the controller 30 transmits a secondary instruction to a bus 5 to instruct the write of data concurrently with a main instruction or when an answer signal is sent to the bus 5. When both memories 32 and 33 receive the secondary instructions from the bus 5, the address held by the device 34 is compared with an address allocated previously via a deciding device 35. Then the data are written when the coincidence is obtained between both addresses. In this case, the bus occupying time can be cut down to about 1/2 if the memory 33 carries out the secondary instruction and the memory 32 does not respectively.