JPS6432352A - Control system for cache memory - Google Patents

Control system for cache memory

Info

Publication number
JPS6432352A
JPS6432352A JP62189417A JP18941787A JPS6432352A JP S6432352 A JPS6432352 A JP S6432352A JP 62189417 A JP62189417 A JP 62189417A JP 18941787 A JP18941787 A JP 18941787A JP S6432352 A JPS6432352 A JP S6432352A
Authority
JP
Japan
Prior art keywords
memory
given
cpu
data
chache
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62189417A
Other languages
Japanese (ja)
Inventor
Satoru Igarashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP62189417A priority Critical patent/JPS6432352A/en
Publication of JPS6432352A publication Critical patent/JPS6432352A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To realize the application of the read data with no access given to a main memory by registering the data given from the main memory with a write request received from a CPU or a channel device into a 2nd chache memory and using said data when a 1st cache memory has a misbit at the time of a read request. CONSTITUTION:The write data given from a channel device 13 connected to a CPU 12 or a magnetic disk device 14 when a block read request is given to a main memory 11 is weitten into a 1st cache memory 21 of a 1st chache control part 23 in the CPU 12 and at the same time registered into a 2nd chache memory 24 of a 2nd cache control part 26. If the memory 21 has a mishit when a memory read request is received from the CPU 12, no access is given to the memory 11 and the desired data is obtained from the memory 24. Then the block read is prevented to the memory 11 and the system throughput is improved.
JP62189417A 1987-07-29 1987-07-29 Control system for cache memory Pending JPS6432352A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62189417A JPS6432352A (en) 1987-07-29 1987-07-29 Control system for cache memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62189417A JPS6432352A (en) 1987-07-29 1987-07-29 Control system for cache memory

Publications (1)

Publication Number Publication Date
JPS6432352A true JPS6432352A (en) 1989-02-02

Family

ID=16240915

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62189417A Pending JPS6432352A (en) 1987-07-29 1987-07-29 Control system for cache memory

Country Status (1)

Country Link
JP (1) JPS6432352A (en)

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