JPS643061B2 - - Google Patents

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Publication number
JPS643061B2
JPS643061B2 JP18998382A JP18998382A JPS643061B2 JP S643061 B2 JPS643061 B2 JP S643061B2 JP 18998382 A JP18998382 A JP 18998382A JP 18998382 A JP18998382 A JP 18998382A JP S643061 B2 JPS643061 B2 JP S643061B2
Authority
JP
Japan
Prior art keywords
semiconductor device
electrode
lead
current
lead electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP18998382A
Other languages
Japanese (ja)
Other versions
JPS5980945A (en
Inventor
Yoshio Nakamura
Susumu Sugyama
Junichi Nishizawa
Tadahiro Oomi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toyota Central R&D Labs Inc
Original Assignee
Toyota Central R&D Labs Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toyota Central R&D Labs Inc filed Critical Toyota Central R&D Labs Inc
Priority to JP57189983A priority Critical patent/JPS5980945A/en
Priority to US06/516,543 priority patent/US4692789A/en
Publication of JPS5980945A publication Critical patent/JPS5980945A/en
Publication of JPS643061B2 publication Critical patent/JPS643061B2/ja
Granted legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64Impedance arrangements
    • H01L23/66High-frequency adaptations
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    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
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    • H01L2223/64Impedance arrangements
    • H01L2223/66High-frequency adaptations
    • H01L2223/6644Packaging aspects of high-frequency amplifiers
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612Auxiliary members for layer connectors, e.g. spacers
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49175Parallel arrangements
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    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • HELECTRICITY
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01042Molybdenum [Mo]
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    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301Thyristor
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    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16195Flat cap [not enclosing an internal cavity]
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Thyristors (AREA)

Description

【発明の詳細な説明】 本発明は高速度で大電流の制御が行える半導体
装置に関し特にその構造の改良に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device capable of controlling a large current at high speed, and particularly to improvements in the structure thereof.

近年、大電力用半導体デバイスを使用して各種
電力機器の高精度および高効率制御が行われるよ
うになつてきており、この分野では高速スイツチ
ングが可能で損失の小さい大電力用半導体デバイ
スが要求されている。仮に、スイツチング速度の
遅い半導体デバイスを使用して大電力のスイツチ
ング制御を行おうとすると、例えば制御周波数が
上げられず人間の可聴周波数領域にとどまり機器
の発生する音が作業者に不快感を与えるとか、半
導体デバイス自身のスイツチング損失が大きく機
器の熱設計が困難になるなどの幣害が生ずること
になる。一方、近年の半導体技術の進歩により大
電力用半導体デバイス自身のスイツチング速度は
飛躍的に向上しており、数100Aの電流を0.1μsec
程度かそれ以下の短い時間でターン・オンおよび
ターン・オフできるようなデバイスが実現されつ
つある。このようなデバイスが前記用途に応用さ
れれば動作周波数を可聴周波数領域より十分高く
しても、スイツチング損失が殆んど問題にならな
いような電力機器が実現可能になる。
In recent years, high-power semiconductor devices have been used to perform high-precision and high-efficiency control of various power equipment, and in this field, high-power semiconductor devices that are capable of high-speed switching and have low loss are required. ing. If a semiconductor device with a slow switching speed were used to perform high-power switching control, for example, the control frequency would not be raised and would remain in the human audible frequency range, causing the sound generated by the equipment to cause discomfort to the worker. , the switching loss of the semiconductor device itself is large, resulting in financial damage such as difficulty in thermal design of the equipment. On the other hand, due to recent advances in semiconductor technology, the switching speed of high-power semiconductor devices themselves has improved dramatically, and the switching speed of several hundred A current can be reduced to 0.1 μsec.
Devices are being realized that can be turned on and turned off in a fraction of a second or less. If such a device is applied to the above-mentioned purpose, it will become possible to realize a power equipment in which switching loss hardly becomes a problem even if the operating frequency is sufficiently higher than the audio frequency range.

ところで、半導体デバイスを実際に使用する時
には、パツケージに封入して使用するのが通常で
ある。第1図に従来のセラミツクシール圧接型パ
ツケージに半導体デバイスをマウントした装置の
分解断面図を示す。この装置は、図示のようにト
ランジスタやサイリスタなどの半導体デバイス
1、モリブデン板2a,2b、銅などの金属導体
ブロツク3a,3b、フランジ4a,4b、溶接
板5a,5b、セラミツク製ケース6、封止パイ
プ兼制御電極取出し穴7、および制御電極リード
8から構成されている。このパツケージは通常円
筒形である。この例は、1ケの半導体デバイス基
板を封入する目的で設計されている。従つて、複
数個の半導体デバイス基板を封入する用途には不
適格である。例えば数100Aの大電力用半導体デ
バイスを実現しようとするとき数10Aから100A
程度の電力用半導体デバイスを複数個並列接続し
て構成すれば1ケ当りの半導体デバイス基板の面
積をそれ程大きくすることもなく実現可能であ
る。通常、1ケの大面積大電流容量の半導体デバ
イス基板を製作するよりも、適正なサイズに分割
した半導体デバイス基板を製造する方が歩留りの
向上が期待できるが、従来のパツケージへ複数個
の半導体デバイス基板を封入することは困難であ
る。
By the way, when a semiconductor device is actually used, it is usually sealed in a package. FIG. 1 shows an exploded sectional view of an apparatus in which a semiconductor device is mounted on a conventional ceramic seal pressure-contact type package. As shown in the figure, this device includes a semiconductor device 1 such as a transistor or a thyristor, molybdenum plates 2a and 2b, metal conductor blocks 3a and 3b such as copper, flanges 4a and 4b, welding plates 5a and 5b, a ceramic case 6, and a seal. It consists of a stop pipe/control electrode extraction hole 7 and a control electrode lead 8. This package is usually cylindrical. This example is designed to encapsulate one semiconductor device substrate. Therefore, it is unsuitable for use in encapsulating a plurality of semiconductor device substrates. For example, when trying to realize a high power semiconductor device of several 100A,
By configuring a plurality of power semiconductor devices connected in parallel, it is possible to achieve this without significantly increasing the area of each semiconductor device substrate. Normally, yields can be expected to improve by manufacturing semiconductor device substrates divided into appropriate sizes rather than manufacturing one large-area, large-current-capacity semiconductor device substrate. Encapsulating device substrates is difficult.

第2図に複数個の半導体デバイス基板をマウン
トした従来のセラミツクケースフラツト型パツケ
ージの例を示す。第2図において半導体デバイス
基板11a,11b、金属ベース12、電極リー
ド13a,13b、セラミツクケース14、ボン
デイングワイヤ15a,15bのように半導体装
置が構成されている。この例では複数個の半導体
デバイス基板がマウントできるように設計されて
いるが、超高周波用半導体装置を目的としてお
り、マウントされる半導体基板が大電力用の半導
体デバイス基板よりかなり小さい上に、電極リー
ド13a,13bは超高周波用回路とのインピー
ダンス整合をとり易くするようにパツケージ外部
へ狭くして取出されている。ここで云う電極リー
ドとはセラミツクに蒸着や印刷によつてメタライ
ズされたところの、半導体デバイス基板上の電極
部とワイヤとかリボンリードで接続されるべき結
合部とセラミツクケースの外部へ取り出されるリ
ド部及び外部のメタライズ部にろう付あるいは溶
接されている電極導体を一括して指している。
FIG. 2 shows an example of a conventional ceramic case flat type package in which a plurality of semiconductor device substrates are mounted. In FIG. 2, a semiconductor device is constructed of semiconductor device substrates 11a, 11b, metal base 12, electrode leads 13a, 13b, ceramic case 14, and bonding wires 15a, 15b. This example is designed to be able to mount multiple semiconductor device substrates, but since it is intended for ultra-high frequency semiconductor devices, the semiconductor substrate to be mounted is considerably smaller than a high-power semiconductor device substrate, and the electrodes The leads 13a and 13b are narrowed and taken out to the outside of the package to facilitate impedance matching with the ultra-high frequency circuit. The term "electrode lead" as used herein refers to the connection part that is metallized on ceramic by vapor deposition or printing and is to be connected to the electrode part on the semiconductor device substrate with a wire or ribbon lead, and the lead part that is taken out to the outside of the ceramic case. and electrode conductors that are brazed or welded to the external metallized part.

通常、大電力用回路は超高周波用回路のインピ
ーダンスより1桁程度以下の小さい値で構成され
るため、第2図の例の半導体装置は数100Aもの
電流を高速にスイツチングするための大電力用半
導体装置としての使用は到底望めない。この事情
は第1図に示した例における制御電極リード8の
様に細いワイヤを使用した場合でも同様である。
Normally, high-power circuits are constructed with an impedance that is one order of magnitude or less smaller than the impedance of ultra-high frequency circuits, so the semiconductor device shown in the example in Figure 2 is designed for high-power applications that rapidly switch currents of several hundred amperes. It cannot be expected to be used as a semiconductor device. This situation is the same even when a thin wire is used like the control electrode lead 8 in the example shown in FIG.

次に大電流の高速スイツチングが可能な半導体
デバイスとして静電誘導サイリスタ(以後SITh
と称す)を例にとり上記の事情を説明する。典型
的なnチヤネルSIThは第3図のようにアノード
A、カソードK、およびゲートGの電極を持つて
おり主電流はアノードAからカソードKへ流れ
る。ゲートGは主電流を流したり遮断したりする
ための制御電極として用いられる。スイツチング
の理想的な動作としては外部より印加されるゲー
ト信号が遅滞なくデバイスのゲート部に伝達さ
れ、これによつて主電流のターン・オン、ター
ン・オフが瞬時になされ、オン時にはアノードと
カソード間の電圧降下がOVに近く、オフ時には
非常に高い電圧を阻止できることである。SITh
はデバイス自身では例えば数100Aを流した時の
アノード、カソード間の電圧降下は約1V程度、
オフ時の阻止電圧は数KV及びターン・オン、タ
ーン・オフは0.1μsec程度かそれ以下の時間での
スイツチングが可能である。このようなSIThを
パツケージに封入したときの集中定数的な等価回
路を第4図に示す。ここでRA,LAは各々アノー
ド電極リードの抵抗、インダクタンス、RK,LK
は各々カソード電極リードの抵抗、インダクタン
ス及びRG,LGは各々ゲート電極リードの抵抗、
インダクタンスである。即ちいずれもSIThを封
入したパツケージ自体のインピーダンスである。
抵抗R、インダクタンスLの導線に時間変化のあ
る電流Iが流れる時の電圧降下はRI+LdI/dtで与 えられる。今、仮に1mΩの抵抗、10nHのイン
ダクタンスを持つ導線に100Aの電流を0.1μsecの
時間で変化させたとすると、殆んどインダクタン
ス成分の効果によりその電圧降下は10Vにもな
る。このような考察に基づいてSIThのスイツチ
ング動作を考察してみよう。一般に半導体デバイ
ス(サイリスタあるいはトランジスタ)を高速に
スイツチングさせる場合、半導体デバイスのゲー
ト電極あるいはベース電極に対し、ターン・オン
時においては高速に電流を供給し所定の電圧に到
達せしめ、逆にターン・オフ時においては高速に
電流を吸引し所定の電圧に到達せしめなければな
らないが、第1図に示した従来例の様に制御電極
リード8が線状の場合とか、第2図に示した従来
例の様に電極リード13a,13bが狭い場合
は、それの持つインピーダンスのために半導体装
置の外部より制御電極リード端に与える信号が半
導体デバイスの制御電極に到達するのに遅れ時間
が生じ、且つインダクタンス成分のためオーバー
シヨートを起す場合もありこれは波形の乱れの原
因となる。とりわけ大電流をスイツチングするサ
イリスタおよびトランジスタをターン・オフさせ
る時には制御電極より大きな電流を吸引しなけれ
ばならないが上記の傾向は顕著に現われて高速動
作の妨げとなる。SIThでは導通時にチヤネル部
に電子とホールが大量に注入されているためター
ンオフ時にそれらをチヤネル部から吸引する必要
がある。ターン・オフの速度を速くしようとすれ
ばする程、瞬時的に制御電極に流れる電流は大き
くなる。この事情は次の(1)式によつて説明され
る。SIThのターン・オフ時間tpffは、略々 tpff=τeff・ln(1+IA/IGP) (1) で与えられる。但し、τeffは実効キヤリヤ寿命、
IAはアノード電流、IGPは遮断時のピークゲート電
流である。(1)式はIGPが大きくなる程tpffは短くな
ることを示している。外部まで含めてSIThのゲ
ートインピーダンスをZGとすれば、IGP・ZGはゲ
ートに加えられる逆ゲートバイアスVGKより大き
くはできない。ZGが小さい程小さなVGKで大きな
IGPを流すことができ高速の遮断が行える。即ち
デバイス自身の制御電極インピーダンスとパツケ
ージの制御電極リードのインピーダンスの和が小
さいことが必然的に要求される。特に高速大電流
のスイツチングではインダクタンス成分の小さい
ことが要求される。ところが前述の様に僅か
10nHのインダクタンスで10Vもの電圧降下があ
るとどうなるか。即ち、半導体デバイスを駆動す
るための駆動回路はこの電圧降下分だけ半導体デ
バイス自身の制御に要する電圧より余計に供給し
なければならないことになる。一方、半導体デバ
イスの制御電極に加えられる電圧は通常高々数
10V程度である。従つて、大電流、高速スイツチ
ングにおいてはインダクタンスが小さくても制御
電極に印加でき得る電圧の大部分をパツケージの
制御電極リードでの電圧降下で占められてしまう
ことになる。
The next semiconductor device capable of high-speed switching of large currents was the electrostatic induction thyristor (SITh).
The above situation will be explained using an example. A typical n-channel SITh has electrodes of an anode A, a cathode K, and a gate G, as shown in FIG. 3, and the main current flows from the anode A to the cathode K. The gate G is used as a control electrode for flowing or cutting off the main current. The ideal operation of switching is that the externally applied gate signal is transmitted to the gate of the device without delay, and as a result, the main current is turned on and off instantly, and when on, the anode and cathode The voltage drop between them is close to OV, and very high voltages can be blocked when they are off. SITh
In the device itself, for example, when several hundred A is applied, the voltage drop between the anode and cathode is about 1V.
The blocking voltage when off is several KV, and switching on and off can be performed in approximately 0.1 μsec or less. FIG. 4 shows a lumped constant equivalent circuit when such SITh is enclosed in a package. Here, R A and L A are the resistance and inductance of the anode electrode lead, respectively, and R K and L K
are the resistance and inductance of the cathode electrode lead, and R G and L G are the resistance and inductance of the gate electrode lead, respectively.
It is inductance. In other words, both are the impedance of the package itself containing SITh.
The voltage drop when a time-varying current I flows through a conductor having a resistance R and an inductance L is given by RI+LdI/dt. Now, if we were to change a current of 100A in a conductor with a resistance of 1mΩ and an inductance of 10nH in a time of 0.1μsec, the voltage drop would be 10V, mostly due to the effect of the inductance component. Let's consider the switching operation of SITh based on these considerations. Generally, when switching a semiconductor device (thyristor or transistor) at high speed, a current is rapidly supplied to the gate electrode or base electrode of the semiconductor device to reach a predetermined voltage when it is turned on, and conversely when it is turned off. Sometimes it is necessary to draw current at high speed to reach a predetermined voltage, but in some cases, the control electrode lead 8 is linear as in the conventional example shown in Fig. 1, or in the conventional example shown in Fig. 2. If the electrode leads 13a and 13b are narrow as in the case of narrow electrode leads 13a and 13b, their impedance causes a delay time for a signal applied to the control electrode lead end from the outside of the semiconductor device to reach the control electrode of the semiconductor device. This component may cause overshoot, which causes waveform disturbance. In particular, when turning off thyristors and transistors that switch large currents, a larger current than the control electrode must be drawn, and the above-mentioned tendency becomes noticeable and hinders high-speed operation. In SITh, a large amount of electrons and holes are injected into the channel part when conduction occurs, so it is necessary to suck them out of the channel part when turn-off. The faster the turn-off speed is attempted, the greater the current instantaneously flowing into the control electrode. This situation is explained by the following equation (1). The turn-off time t pff of SITh is approximately given by t pff = τ eff · ln (1 + I A /I GP ) (1). However, τ eff is the effective carrier life,
I A is the anode current and I GP is the peak gate current at cut-off. Equation (1) shows that the larger I GP becomes, the shorter t pff becomes. If the gate impedance of SITh including the outside is Z G , then I GP Z G cannot be greater than the reverse gate bias V GK applied to the gate. The smaller the Z G , the smaller the V GK and the larger the
It can flow I GP and perform high-speed shutoff. That is, it is necessarily required that the sum of the control electrode impedance of the device itself and the impedance of the control electrode lead of the package be small. In particular, high-speed, large-current switching requires a small inductance component. However, as mentioned above, there are only a few
What happens if there is a voltage drop of 10V with an inductance of 10nH? In other words, the drive circuit for driving the semiconductor device must supply more voltage than the voltage required to control the semiconductor device itself by this voltage drop. On the other hand, the voltage applied to the control electrode of a semiconductor device is usually at most several
It is about 10V. Therefore, in high-current, high-speed switching, even if the inductance is small, most of the voltage that can be applied to the control electrode is accounted for by the voltage drop at the control electrode lead of the package.

今、ここで制御電極リードの自己インダクタン
スを考えてみると直径2r、長さlの線が有する自
己インダクタンスLは L=μol/2π(ln2l/r−1)(H) (2) 幅W、長さlの板状の導体が有する自己インダ
クタンスLは L=μol/2π(ln2l/W+1/2+W/3l)(H)(3
) で与えられる。2r=1mm、l=50mm、及びW=5
mm、l=50mmとするとLは各々43nH及び35.3nH
にもなり、制御電極を考えただけでも到底高速大
電流のスイツチングは行えないことになる。
Now, if we consider the self-inductance of the control electrode lead, the self-inductance L of a wire with diameter 2r and length l is L = μol/2π (ln2l/r-1) (H) (2) Width W, The self-inductance L of a plate-shaped conductor of length l is L=μol/2π(ln2l/W+1/2+W/3l)(H)(3
) is given by 2r=1mm, l=50mm, and W=5
When mm and l=50mm, L is 43nH and 35.3nH, respectively.
Therefore, it is impossible to perform high-speed, large-current switching just by considering the control electrode.

次にカソード電極及びアノード電極を考えて見
よう。スイツチングされるべき主電流はこれらの
電極に流れることになるから数100Aもの電流に
耐え得る面積を持つべきであることは当然である
が、自己インダクタンスの効果を考察すると、次
の様な不都合が生ずることになる。今制御信号に
よつてSIThがオーン・オンの過程にあるとする。
SIThをターン・オンしようとするときはター
ン・オフ時に与えているゲートバイアス電圧
VGKpffからターン・オンに導くための十分なゲー
トバイアス電圧VGKpoまでゲート電圧を増加させ
なければならない。この時のゲートバイアス電圧
とはSIThデバイス自身のカソード電極を基準に
したゲート電極の電圧である。ゲート電圧が
VGKpffからVGKpoに増加する過程で主電流が流れ始
めるとカソード電極リードのインダクタンスによ
つてLKdl/dtだけデバイスのカソード電圧が上昇す る。このカソード電極の電圧上昇によつて、カソ
ードに対するゲート電圧VGKは相対的に低下する
ことになりターン・オン時間を遅らせる。即ち、
インダクタンスによつて負帰還作用が生ずる訳で
ある。これはターン・オフ過程でも符号を逆にし
て考えれば全く同じことが云える。このことはゲ
ート駆動回路に更に余計な電圧供給能力を持たせ
なければいけないことを意味する。電極リードと
してかなり幅広いと思われるW=50mm、l=20mm
の場合、(3)式を用いて己インダクタンスLを計算
してみると16.1nHとなり、かなり小さくはなる。
仮に、100Aの電流を0.1μsecの時間で流したとす
ると電圧降下分は16.1Vにもなり、このような考
え方ではとても大電流の高速スイツチングはなし
得ないことになる。またアノード電極リードを考
えて見てもその自己インダクタンスを考えただけ
では到底高速に何百Vあるいは何千Vもの高圧か
ら1V程度の低いON電圧に到達できないことが上
述の場合と全く同様に説明される。このように自
己インダクタンスのみを考えた第4図のような積
中定数モデルの概念では高速大電流のスイツチン
グは実現されず分布定数回路として伝送線路的に
パツケージを構成しなければならない。
Next, let's consider the cathode electrode and the anode electrode. Since the main current to be switched will flow through these electrodes, it is natural that they should have an area that can withstand a current of several hundred amperes, but when considering the effect of self-inductance, the following disadvantages arise. will occur. Suppose that SITh is now in the process of being turned on by the control signal.
When trying to turn on SITh, apply the gate bias voltage when turning off
The gate voltage must be increased from V GKpff to a sufficient gate bias voltage V GKpo to induce turn-on. The gate bias voltage at this time is the voltage of the gate electrode based on the cathode electrode of the SITh device itself. gate voltage
When the main current begins to flow in the process of increasing from V GKpff to V GKpo , the cathode voltage of the device increases by L K dl/dt due to the inductance of the cathode electrode lead. Due to this increase in the voltage of the cathode electrode, the gate voltage V GK with respect to the cathode decreases relatively, thereby delaying the turn-on time. That is,
This is why the inductance causes a negative feedback effect. The same thing can be said for the turn-off process if the sign is reversed. This means that the gate drive circuit must have additional voltage supply capability. W = 50mm, L = 20mm, which seems to be quite wide as an electrode lead.
In this case, when calculating the self-inductance L using equation (3), it becomes 16.1 nH, which is quite small.
If a current of 100A were to flow in a time of 0.1μsec, the voltage drop would be 16.1V, which means that high-speed switching of extremely large currents would not be possible with this kind of thinking. Also, even if we consider the anode electrode lead, it is explained in exactly the same way as in the above case that it is impossible to quickly reach an ON voltage as low as 1V from a high voltage of hundreds or thousands of V just by considering its self-inductance. be done. In this way, high-speed, large-current switching cannot be achieved with the concept of a multi-layer constant model as shown in FIG. 4, which considers only self-inductance, and the package must be constructed in the form of a transmission line as a distributed constant circuit.

本発明は上記のような点に鑑みパツケージの全
ての電極リードを板状に幅広くし所望の低インピ
ーダンスを得易くし、大電流の高速動作が行える
半導体装置を提供しようとするものである。
In view of the above points, the present invention aims to provide a semiconductor device in which all the electrode leads of the package are made wide in the form of a plate, making it easier to obtain a desired low impedance, and capable of high-speed operation with a large current.

以下、図面を参照しながら本発明を説明する。
第5図に本発明の全電極リードを板状にしてイン
ダクタンス成分を減少させた半導体装置の一実施
例の分解上面図aと分解断面図bを示す。この装
置はサイリスタ、トランジスタ等の半導体デバイ
ス21a,21b…21j、モリブデン板22
a,22b…22j、それ自体が第一の電極とな
り、前記半導体デバイスの第二主表面(図では下
方の表面)に前記モリブデン板で接続されている
導体ベース23、前記半導体デバイスの第一の主
表面(図では上方の表面)に接続される第二の電
極となる導体板リード24、同じく第三の電極と
なる導体板リード25、ボンデイングワイヤリー
ド(あるいはリボンリード)26a,26b、お
よびセラミツク等の絶縁体のケース27等によつ
て構成されている。ここで電極となる導体板リー
ド24,25はセラミツク等の絶縁体に蒸着や印
刷によつてメタライズされたところの半導体デバ
イス基板上の電極部とワイヤとかリボンリードで
接続されるべき結合部とケースの外部へ取り出さ
れるリード部及び外部のメタライズ部にろう付あ
るいは溶接されている電極導体を一括して指して
いる。もちろんこれらは一枚の導体板でも良い。
導体ベース23は通常電気伝導度も熱伝導度も大
きい金属で構成される。またモリブデン板22を
複数個設けた場合について示したが、モリブデン
板は細長い一枚の板でもよい。このように電極導
体ベース23および導体板リード24,25は収
容される複数個の半導体デバイス基板の1ケの一
辺の寸法の収容されているデバイスの個数分の和
より広くなつており、導体板リード24,25は
互いの間隔より広い幅を持つている。電極導体ベ
ース23は収容されるデバイス全部をその上にマ
ウントでき、導体板リード24,25は全部のデ
バイスの電極部と多数の平行なボンデイングワイ
ヤリード26a,26bにより電気的に結合され
ている。この例では、半導体デバイス21a,2
1b,…21jてすべて切離されている例につい
て述べたが、必ずしもこうする必要はない。シリ
コンウエハ上に、半導体デバイス21a,21
b,…21jを細長く形成して、一体で構成して
よいし、もちろん、所定の個数ずつ一体構成にし
て細長く配置してもよい。これらのことは、半導
体プロセスにおける歩留りの問題と、半導体デバ
イスをモリブデン板に均一にメタライズする時の
歩留り等アセンブル工程の歩留りからもつとも低
価格になるよう各技術レベルから判断して決めれ
ばよい。要するに、高速で変化する電流が局所に
集中して流れてインダクタンス分を増さないよう
に、拡がつて流れるように配置することが重要な
のである。第5図で、導体板リード24,25と
半導体デバイスの間はワイヤーリードあるいはリ
ボンリードにより接続されている。第5図の構成
の中では、電流がもつとも集中して流れる部分で
ある。したがつて、導体板リード24及び25と
半導体デバイス21の間は、物理的配置が許す限
り狭いことが必要である。また、半導体デバイス
自身も、導体板リード24と25を結ぶ方向があ
まりに長いと、半導体デバイス上の金属電極配線
の持つインダクタンスが問題になるためそれほど
長くはできない。しかも、大電流を流そうとする
ときには、半導体デバイスの全面積は大きくしな
ければならない。結局、第5図aに示すように上
下方向に細長い配置にしなければならない。パツ
ケージとしては、導体板リード24と25の電流
の流れの方向に対して直角方向の幅が導体板リー
ド24と25の間隔にくらべて広くなるような構
成にしなければならない。たとえば、カソード、
アノード間隔450μm、P+ゲート拡散深さ4μm、
P+ゲート、ゲート間隔1.5μmのストライプ構造に
基本チヤネルが形成されたSIThでは、チヤネル
部の電流密度800A/cm2で、オン電圧1.0〜1.2Vの
動作が実現される。平均電流100AのSIThを構成
しようとするとその半導体デバイスのチツプサイ
ズは約7×40mm2となる。即ち、導体板リード24
と25を結ぶ方向の半導体デバイスの長さは7
mm、それと垂直方向のいわゆる電流の流れる方向
と垂直方向のデバイスの幅は40mmというようにな
る。その時の導体板リード24と25の間隔は
略々10mm、電流の流れる方向と垂直な方向のリー
ドの幅は略々40mmというように形成されている。
The present invention will be described below with reference to the drawings.
FIG. 5 shows an exploded top view (a) and an exploded cross-sectional view (b) of an embodiment of a semiconductor device in which all electrode leads of the present invention are made into plate shapes to reduce the inductance component. This device includes semiconductor devices 21a, 21b...21j such as thyristors and transistors, and a molybdenum plate 22.
a, 22b...22j, a conductor base 23 which itself becomes a first electrode and is connected to the second main surface (lower surface in the figure) of the semiconductor device with the molybdenum plate; A conductor plate lead 24 serving as a second electrode connected to the main surface (the upper surface in the figure), a conductor plate lead 25 serving as a third electrode, bonding wire leads (or ribbon leads) 26a, 26b, and ceramic It is composed of a case 27 made of an insulator such as the like. Here, the conductor plate leads 24 and 25, which serve as electrodes, are metalized by vapor deposition or printing on an insulator such as ceramic, and are connected to the electrode parts on the semiconductor device substrate by wires or ribbon leads, and the case. It collectively refers to the lead part taken out to the outside and the electrode conductor brazed or welded to the external metallized part. Of course, these may be a single conductor plate.
The conductor base 23 is usually made of metal having high electrical conductivity and high thermal conductivity. Further, although the case where a plurality of molybdenum plates 22 are provided is shown, the molybdenum plate may be a single elongated plate. In this way, the electrode conductor base 23 and the conductor plate leads 24, 25 are wider than the sum of the dimensions of one side of the plurality of semiconductor device substrates accommodated, and the conductor plate The leads 24 and 25 have a width greater than the distance between them. The electrode conductor base 23 can mount all the devices accommodated thereon, and the conductor plate leads 24, 25 are electrically coupled to the electrode portions of all the devices by a number of parallel bonding wire leads 26a, 26b. In this example, semiconductor devices 21a, 2
1b, . . . 21j are all separated, but it is not necessary to do so. Semiconductor devices 21a, 21 are placed on the silicon wafer.
b, . . . 21j may be formed into a long and thin piece and configured integrally, or, of course, a predetermined number of pieces may be formed into a single piece and arranged in a long and thin manner. These matters can be determined based on each technology level so that the cost can be kept low considering the yield issues in the semiconductor process and the yield of the assembly process such as the yield when uniformly metalizing the semiconductor device onto the molybdenum plate. In short, it is important to arrange the device so that the rapidly changing current spreads out and does not flow locally and increase the inductance. In FIG. 5, the conductor plate leads 24, 25 and the semiconductor device are connected by wire leads or ribbon leads. In the configuration shown in FIG. 5, this is the part where the current flows in a concentrated manner. Therefore, it is necessary that the distance between the conductor plate leads 24 and 25 and the semiconductor device 21 be as narrow as the physical arrangement allows. Further, if the semiconductor device itself is too long in the direction connecting the conductor plate leads 24 and 25, the inductance of the metal electrode wiring on the semiconductor device will become a problem, so it cannot be made that long. Moreover, when a large current is to flow, the total area of the semiconductor device must be increased. In the end, the arrangement must be elongated in the vertical direction as shown in FIG. 5a. The package must be constructed such that the width of the conductor plate leads 24 and 25 in the direction perpendicular to the direction of current flow is wider than the distance between the conductor plate leads 24 and 25. For example, cathode,
Anode spacing 450μm, P + gate diffusion depth 4μm,
In SITh, in which a basic channel is formed in a stripe structure with a P + gate and a gate spacing of 1.5 μm, operation with an on-voltage of 1.0 to 1.2 V is achieved at a current density of 800 A/cm 2 in the channel portion. If an SITh with an average current of 100 A is constructed, the chip size of the semiconductor device will be approximately 7 x 40 mm 2 . That is, the conductor plate lead 24
The length of the semiconductor device in the direction connecting 25 and 25 is 7
mm, and the width of the device in the direction perpendicular to the so-called current flow direction is 40 mm. At this time, the distance between the conductor plate leads 24 and 25 is approximately 10 mm, and the width of the leads in the direction perpendicular to the current flow direction is approximately 40 mm.

このような構成を有するパツケージは通常広い
導体板上に実装される。したがつて、制御電極リ
ード部もアノードやカソード電極部も伝送線路的
な構成になる。このように伝送線路構成になると
自己インダクタンスは殆んど効果を持たず相互イ
ンダクタンスが効果を持つようになる。
Packages with such a configuration are usually mounted on wide conductor plates. Therefore, both the control electrode lead portion and the anode and cathode electrode portions have a transmission line-like configuration. In such a transmission line configuration, self-inductance has almost no effect, and mutual inductance has an effect.

従来の線状電極リードや狭く設計されている板
状電極リードと本発明の広い板状電極リードとの
伝送線路的な比較を次に述べる。直径2rの線が空
気中で広い導体板として平行に距離Dだけ離れて
あるときの特性インピーダンスZ0は、 である。幅Wの板状導体が空気中で広い導体板上
に平行に距離Dだけ離れてあるときの特性インピ
ーダンスZ0は近似的に、 Z0≒377/W/D{1+1.735(W/D)-0.836}〔Ω〕
……(5) で与えられる。
A comparison of transmission lines between conventional linear electrode leads or narrowly designed plate electrode leads and the wide plate electrode lead of the present invention will be described below. The characteristic impedance Z 0 when a wire with a diameter of 2r is placed in parallel as a wide conductor plate in the air and separated by a distance D is: It is. The characteristic impedance Z 0 when a plate-shaped conductor with a width W is placed parallel to a wide conductor plate in the air and separated by a distance D is approximately Z 0 ≒377/W/D {1+1.735 (W/D ) -0.836 }[Ω]
... is given by (5).

r=0.5mmの径の場合、D=5mmとして(4)式に
代入すると、 Z0≒180〔Ω〕 ……(6) W=5mm、D=5mmのときの狭い板状の場合、
(5)式より、 Z0≒138〔Ω〕 ……(7) W=50mm、D=5mmのときの広い板状の場合、
(5)式より、 Z0≒30〔Ω〕 ……(8) となる。
In the case of a diameter of r = 0.5 mm, when D = 5 mm and substituted into equation (4), Z 0 ≒ 180 [Ω] ... (6) In the case of a narrow plate shape when W = 5 mm and D = 5 mm,
From formula (5), Z 0 ≒138 [Ω] ...(7) In the case of a wide plate when W = 50 mm and D = 5 mm,
From formula (5), Z 0 ≒30 [Ω] ...(8).

(6),(7)、および(8)式から明らかなように幅を広
くした平板の電極構造のものの方がインピーダン
スが線状のものや狭い板状のものよりかなり小さ
い。大電力デバイス、特に大電流のデバイスを使
用するときにはデバイスの入力インピーダンス、
出力インピーダンスともに小さくなるので入出力
回路のインピーダンスも小さい方が望ましいわけ
である。とりわけ大電流のスイツチングをSITh
などの半導体デバイスで高速に行う場合にはター
ンオフ時に大きなゲート電流を吸引する必要があ
るから、本発明による全電極リードのインピーダ
ンスを低減した効果は大きい。
As is clear from equations (6), (7), and (8), the impedance of a wide plate electrode structure is considerably smaller than that of a linear electrode structure or a narrow plate electrode structure. When using high power devices, especially high current devices, the input impedance of the device,
Since both the output impedance becomes small, it is desirable that the impedance of the input/output circuit is also small. Particularly suitable for high current switching
When performing high-speed operation with a semiconductor device such as, it is necessary to attract a large gate current at turn-off, so the effect of reducing the impedance of all electrode leads according to the present invention is significant.

第5図の実施例は半導体デバイス基板が、それ
自体電極となる導体ベースの上にマウントされて
いる例であるが、使用目的によつては半導体装置
を固定し熱す逃す金属ベースと半導体デバイス基
板をマウントし電極となる導体板と電気的に絶縁
されている方が都合が良い場合がある。その例を
第6図に示す。また、電極の取り出し方向が同一
であるよりも、例えば他の電極と90゜の角をなし
て取り出した方が使い易い場合もある。その例を
第7図に示す。第6図及び第7図の実施例では第
5図の実施例と同じ部分には同じ記号を用いてい
る。第6図及び第7図の29は炭化ケイ素、ベリ
リヤやアルミナ等の絶縁板、30は銅などの金属
ベースである。
The embodiment shown in FIG. 5 is an example in which a semiconductor device substrate is mounted on a conductive base that itself serves as an electrode, but depending on the purpose of use, a metal base that fixes the semiconductor device and releases heat, and the semiconductor device In some cases, it may be more convenient to mount the substrate and electrically insulate it from the conductor plate that serves as the electrode. An example is shown in FIG. Furthermore, it may be easier to use if the electrodes are taken out at a 90° angle with other electrodes, for example, rather than taken out in the same direction. An example is shown in FIG. In the embodiment shown in FIGS. 6 and 7, the same symbols are used for the same parts as in the embodiment shown in FIG. In FIGS. 6 and 7, 29 is an insulating plate made of silicon carbide, beryllia, alumina, etc., and 30 is a metal base such as copper.

SIThにしろ、バイポーラモードSIT(BSIT)
にしろ、あるいは他のバイポーラトランジスタ
(BJT)やゲートターンオフサイリスタ(GTO)
にしろ、ソース、エミツタもしくはカソードとい
つたキヤリヤを注入する主電極のごく近傍にゲー
トもしくはベースといつた制御電極が設けられる
のが普通である。したがつて第5図aに示された
半導体装置の分解上面図において、導体板リード
24,25は各々制御電極、キヤリヤ注入主電極
に接続されるリードとなる。導体ベース23が、
デバイスのドレイン、コレクタもしくはアノード
といつたキヤリヤ引き出し主電極のリードとなる
わけである。
SITh, bipolar mode SIT (BSIT)
or any other bipolar transistor (BJT) or gate turn-off thyristor (GTO)
However, it is common to have a control electrode, such as a gate or base, in close proximity to a main carrier-injecting electrode, such as a source, emitter, or cathode. Therefore, in the exploded top view of the semiconductor device shown in FIG. 5a, the conductor plate leads 24 and 25 become leads connected to the control electrode and the carrier injection main electrode, respectively. The conductor base 23 is
This serves as the lead for the carrier extraction main electrode, such as the drain, collector, or anode of the device.

ところで、通常大電力高周波制御回路において
は、キヤリヤ注入電極を共通電位端子とする回路
構成にすることが多い。たとえば、導体板リード
25をキヤリヤ注入主電極とすると、導体板リー
ド25が第5,6,7図のような形状に構成され
ていても、実際に回路を形成することは可能であ
る。しかし、相当程度の工夫が必要なこともまた
事実である。回路構成のことまで考えると、第8
図あるいは第9図のようにパツケージを形成して
おくと回路の構成が容易になる。
By the way, in normal high-power high-frequency control circuits, the circuit structure is often such that the carrier injection electrode is used as a common potential terminal. For example, if the conductor plate lead 25 is used as a carrier injection main electrode, it is possible to actually form a circuit even if the conductor plate lead 25 has a shape as shown in FIGS. 5, 6, and 7. However, it is also true that a considerable degree of ingenuity is required. If you think about the circuit configuration, the 8th
If the package is formed as shown in the figure or FIG. 9, the construction of the circuit becomes easy.

第8図では、基本的構造は第5,6,7図と同
じであるが、キヤリヤ注入主電極を共通電位端子
とする時に、回路的配置が容易になるようになさ
れたものである。第8図において、31は銅など
の金属、32も銅などの金属板である。33はセ
ラミツク等の絶縁物である。このような構造の半
導体装置は、共通電位端子となるキヤリヤ注入主
電極を、回路中の共通電位となる大面積の銅板な
どの、金属板32を接着すればよいから配置がき
わめて簡単になる。制御電極駆動回路と、主電極
間回路を、たとえば左右に分けてきれいに配置で
きる。すべてが広い共通電位銅板上に構成できる
から、分布定数回路配置が容易になる。半導体装
置が数1000Vの高耐圧デバイスとなる場合には、
制御電極となる導体板リード24とキヤリヤ引き
出し主電極となる導体板リード23を第8図で下
方向に垂直に曲げておくと回路配置がし易くな
る。
In FIG. 8, the basic structure is the same as in FIGS. 5, 6, and 7, but the circuit layout is simplified when the carrier injection main electrode is used as a common potential terminal. In FIG. 8, 31 is a metal such as copper, and 32 is also a metal plate such as copper. 33 is an insulating material such as ceramic. In a semiconductor device having such a structure, the carrier injection main electrode, which serves as a common potential terminal, can be simply bonded to a metal plate 32, such as a large-area copper plate, which serves as a common potential in the circuit, making the arrangement extremely simple. The control electrode drive circuit and the main inter-electrode circuit can be neatly arranged, for example, separated into left and right sides. Since everything can be constructed on a wide common potential copper plate, distributed constant circuit layout is facilitated. When a semiconductor device becomes a high-voltage device with several thousand volts,
If the conductor plate lead 24 serving as the control electrode and the conductor plate lead 23 serving as the carrier lead-out main electrode are bent vertically downward as shown in FIG. 8, the circuit arrangement will be easier.

第8図の例では、デバイスの放熱は22,2
3,29,30を通してだけほぼ行なわれる。も
う一方の面からも放熱を行えるようにすること
も、もちろん可能である。その例が第9図であ
る。孫9図は半導体デバイスが複数チツプでな
く、一体構成の場合に使用し易い構造になつてい
る。即ち、半導体デバイスのキヤリヤ注入主電極
もモリブデン板34を介して、導体板リード35
に直接接続されている。36,37はセラミツク
などの絶縁物である。これらの絶縁物も熱伝導の
高いベリリヤや炭化ケイ素で作られていることが
望ましい。第9図の構造ではキヤリヤ注入主電極
がモリブデン板、あるいは必要ならさらに銅板を
介して主電極となる導体板リード35に直結され
ており、ワイヤリードやリボンリードが存在しな
いため、インダクタンスが一層小さくなつて、き
わめて望ましい。共通電位端子となる電極のイン
ダクタンスは既に述べたように負帰還作用を有す
るので、できるだけ小さいことが望ましい。
In the example of Figure 8, the heat dissipation of the device is 22,2
This is mostly done only through 3, 29, and 30. Of course, it is also possible to dissipate heat from the other side. An example is shown in FIG. Figure 9 has a structure that is easy to use when the semiconductor device is not composed of multiple chips but is integrated. That is, the carrier injection main electrode of the semiconductor device is also connected to the conductor plate lead 35 via the molybdenum plate 34.
connected directly to. 36 and 37 are insulators such as ceramics. These insulators are also preferably made of beryllia or silicon carbide, which have high thermal conductivity. In the structure shown in Fig. 9, the carrier injection main electrode is directly connected to the conductor plate lead 35 which becomes the main electrode via a molybdenum plate or, if necessary, a copper plate, and there is no wire lead or ribbon lead, so the inductance is even smaller. As a result, it is extremely desirable. Since the inductance of the electrode serving as the common potential terminal has a negative feedback effect as described above, it is desirable that it be as small as possible.

第9図の構造の半導体装置は、インダクタンス
がきわめて小さくて高速大電流スイツチングに向
くと同時に、回路構成がし易いこと、及び放熱の
点でもきわめて優れている。
The semiconductor device having the structure shown in FIG. 9 has an extremely small inductance and is suitable for high-speed, large-current switching, and is also excellent in terms of ease of circuit construction and heat dissipation.

第5,6,7,8,9図においては、本発明の
主眼である電極リード構造をわかり易いように、
例えばシール部等の詳細を省いて要部のみを描い
てある。第5図に示した一実施例の具体的な形状
の一例を第10図に示す。なお、制御電極となる
導体板リード24に流れる電流は相対的に導体板
リード25の電流より小さいので、導体板リード
24の幅は導体板リード25より若干狭くしても
よい。
In Figures 5, 6, 7, 8, and 9, the electrode lead structure, which is the main focus of the present invention, is shown for easy understanding.
For example, only the main parts are depicted, omitting details such as seals. An example of a specific shape of the embodiment shown in FIG. 5 is shown in FIG. 10. Note that since the current flowing through the conductor plate lead 24 serving as the control electrode is relatively smaller than the current through the conductor plate lead 25, the width of the conductor plate lead 24 may be made slightly narrower than the conductor plate lead 25.

本発明の半導体装置においては、いずれにして
も、半導体デバイス基板は、複数チツプになるに
しろ、一体構造になるにしろ略々矩形状に配置さ
れ、その長辺方向にわたつて導体板リードの幅方
向の端面が配置され、その導体板リードの幅を前
記矩形における長辺方向の長さより大きくなさ
れ、その導体板リードの幅は相対向する導体板リ
ード間の間隔より広く構成されているわけであ
る。
In the semiconductor device of the present invention, the semiconductor device substrate is arranged in a substantially rectangular shape, whether it has a plurality of chips or an integrated structure, and the conductor plate leads extend along the long sides of the semiconductor device substrate. The end faces in the width direction are arranged, and the width of the conductor plate lead is made larger than the length of the long side of the rectangle, and the width of the conductor plate lead is wider than the interval between the opposing conductor plate leads. It is.

本発明による幅が広い電極の効果を示す例とし
て、高周波用コンデンサとして市販されている耐
圧2000V,10μFのコンデンサ(60×100×150mm3
容積、端子が上部に2個設けられている)を用い
て行なつた実験例を次に説明する。本発明に基づ
く工夫を施した構造の半導体デバイスTを用いて
第11図の高周波大電流のスイツチング回路を構
成した。この半導体デバイスは200Aの電流をオ
ン・オフできるものである。実験は電流スイツチ
ングを観測しようとするものであるためRL=0,
RM=0.01Ωとしてある。
As an example showing the effect of the wide electrode according to the present invention, a 2000V, 10μF capacitor (60 x 100 x 150 mm 3
An example of an experiment carried out using a volume (with two terminals provided at the top) will be described below. A high frequency, large current switching circuit shown in FIG. 11 was constructed using a semiconductor device T having a structure based on the present invention. This semiconductor device can turn on and off a current of 200A. Since the experiment aims to observe current switching, R L =0,
R M =0.01Ω.

先ず第11図の回路において、コンデンサCD
とCgに前記の高周波用コンデンサを用い、この
端子には幅2cmの網状の線で片側約10cmずつ全体
で20cmの配線を施した。この回路構成で得られる
電流のスイツチング波形は第12図aのようなも
のであつた。即ち、立上り、立下りともに遅く
て、しかも電流が殆んど流れないという結果にな
つた。このような結果になつたのはコンデンサに
配線した幅の広いリード線にインダクタンスによ
る電圧降下が生じてしまつているからである。次
に、両側にリードの出ている容積の小さなコンデ
ンサを10ケ並列にならべて、300μFを構成した。
リードのインダクタンスが減少すると同時に電流
が細い部分に集中して流れることがなくなるため
実効的なインダクタンスはさらに減少している。
その時の電流波形は第12図bのようになる。
First, in the circuit of Figure 11, capacitor C D
The above-mentioned high frequency capacitors were used for C and C g , and these terminals were wired with 2 cm wide mesh wires, approximately 10 cm on each side and 20 cm in total. The current switching waveform obtained with this circuit configuration was as shown in FIG. 12a. That is, both the rise and fall were slow, and the result was that almost no current flowed. This result is due to the voltage drop caused by inductance in the wide lead wire connected to the capacitor. Next, I connected 10 small capacitors with leads on both sides in parallel to form a 300μF capacitor.
At the same time as the lead inductance decreases, the effective inductance further decreases because the current no longer flows concentrated in a narrow portion.
The current waveform at that time is as shown in FIG. 12b.

200Aの電流スイツチングが0.15μsec以下のス
イツチング時間で達成されている。らに第11図
のCDのコンデンサ部を工夫し、リードインダク
タンスを殆んど持たない回路構成に第11図の回
路を形成し、第10図の実施例のパツケージ中に
7×40mm2のチツプサイズのバイポーラモードSIT
(BSIT)を挿入した本発明の半導体装置を用い
て、高周波大電流のスイツチングを行なわせたと
ころ、オン電圧0.7V、電流100A、ターン・オン
時間0.1μsec、ターン・オフ時間10nsecの記録的
な大電流大速スイツチングが実現された。この時
の波形を第13図に示す。100A,10nsecという
スイツチングは、未だかつて記録されたことのな
い高速度スイツチングである。この時の電圧振巾
は300V、負荷抵抗RLは3Ωであつた。従来型のパ
ツケージに上記BSITを封入した半導体装置では
とても実現できない値である。
Current switching of 200A is achieved with a switching time of less than 0.15μsec. Furthermore, the capacitor section of C D in Fig. 11 was devised to form the circuit shown in Fig. 11 in a circuit configuration that has almost no lead inductance, and a 7 x 40 mm 2 capacitor was added in the package of the embodiment shown in Fig. 10. Chip-sized bipolar mode SIT
When high-frequency, large-current switching was performed using the semiconductor device of the present invention into which (BSIT) was inserted, a record-setting on-voltage of 0.7V, current of 100A, turn-on time of 0.1μsec, and turn-off time of 10ns was achieved. High-current, high-speed switching was realized. The waveform at this time is shown in FIG. Switching at 100A and 10nsec is a high-speed switching that has never been recorded before. The voltage amplitude at this time was 300V, and the load resistance R L was 3Ω. This is a value that cannot be achieved with a semiconductor device in which the above-mentioned BSIT is enclosed in a conventional package.

このように本発明により電流を分散させインダ
クタンスを低下せしめた効果は本実験結果に顕著
に現われている。また本実験結果は高速大電流の
スイツチングが行える半導体デバイスができても
それを封入するパツケージを含めた回路の構成方
法及び使用するコンデンサや抵抗等の回路を構成
する素子の構造が大電流高速のスイツチングに適
したものでなければ、半導体デバイスの高速性を
活かすことができないことをも示している。
As described above, the effect of dispersing the current and lowering the inductance according to the present invention is clearly seen in the results of this experiment. The results of this experiment also show that even if a semiconductor device capable of high-speed, high-speed switching is created, the method of configuring the circuit, including the package that encloses it, and the structure of the elements that make up the circuit, such as the capacitors and resistors used, are This also shows that unless the device is suitable for switching, it will not be possible to take advantage of the high-speed performance of semiconductor devices.

本発明の半導体装置は、回路構成に配慮すれば
数10Aから数1000Aといつた大電流がきわめて高
速にスイツチングできることになり、大電力の制
御が効率よく行え、しかもその動作周波数が容易
に可聴周波数領域を超えた領域に持ち込めるため
作業者に不快感を与えることもなく、スイツチン
グ損失も小さくできその上圧接型パツケージのよ
うに大きな荷重をかける必要もなく取扱いが簡単
で実装設計を容易にし、その工業的価値はきわめ
て大きい。
The semiconductor device of the present invention can switch large currents ranging from several tens of amperes to several thousand amperes at extremely high speeds if the circuit configuration is considered, and can efficiently control large amounts of power.Moreover, the operating frequency can easily be adjusted to an audible frequency. Because it can be brought into an area beyond the specified area, it does not cause discomfort to the operator, reduces switching loss, and does not require heavy loads unlike pressure-welding type packages, making it easy to handle and mounting design. The industrial value is extremely large.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のセラミツクシール圧接型パツケ
ージに半導体デバイスをマウントした装置の分解
断面図、第2図は複数個の半導体デバイス基板を
マウントした従来のセラミツクケースフラツト型
パツケージの例を示すもので、aは分解上面図、
bは分解断面図である。第3図はnチヤネル
SIThを記号的に示す図、第4図はそのSIThをパ
ツケージに封入したときの集中定数的な等価回路
である。第5図は、本発明の全電極リードを板状
にしてインダクタンス成分を減少させた半導体装
置の一実施例の分解上面図aと分解断面図bであ
る。第6図は、半導体装置を固定し熱を逃がす金
属ベースと半導体デバイス基板をマウントし電極
となる導体とを電気的に絶縁した本発明の他の実
施例の分解断面図、第7図は電極の取り出し方向
を第6図のように同一とせず、90゜の角をなして
取り出す本発明の他の実施例の分解断面図であ
る。第8図はキヤリヤ注入主電極を共通電位端子
とするときに回路的配置が容易になるよう構成し
たさらに他の実施例を示すものである。第9図は
半導体デバイスのキヤリヤ注入主電極をモリブデ
ン板を介して導体板リードに直接接続された構成
を持つた本発明の他の実施例を示すものである。
第10図は第5図の実施例の具体例な形状を示す
斜視図である。第11図は本発明の半導体装置の
特性を調べるための回路、第12図aは第11図
の回路においてコンデンサCD,Cgのリード線を
インダクタンスが大きくなるようにした場合のス
イツチング波形、同図bはコンデンサCD,Cg
リード線を実効的にインダクタンスが小さくなる
ように構成した場合のスイツチング波形を示すも
のである。第13図は第10図の実施例のパツケ
ージ中にBSITを挿入した本発明の半導体装置を
用い、第11図の回路によつて大電流のスイツチ
ングを行なつたときのスイツチング波形を示すも
のである。 1,11a,11b,21a,21b,21j
……半導体デバイス基板、2a,2b,22a,
22b,22j,34……モリブデン板、3a,
3b……金属導体ブロツク、4a,4b……フラ
ンジ、5a,5b……溶接板、6……セラミツク
製ケース、7……封止パイプ兼制御電極取出し
穴、8……制御リード電極、12……金属ベー
ス、13a,13b……電極リード、14……セ
ラミツクケース、15a,15b,26a,26
b……ボンデイングワイヤ(またはリボンリー
ド)、23……導体ベース、24,25……導体
板リード、27……絶縁体ケース、29……絶縁
板、30……金属ベース、31……銅などの金
属、32……金属板、33,36,37……絶縁
物、35……導体板リード、38……シール板。
Figure 1 is an exploded cross-sectional view of a device in which a semiconductor device is mounted on a conventional ceramic seal press-contact type package, and Figure 2 shows an example of a conventional ceramic case flat type package in which multiple semiconductor device substrates are mounted. , a is an exploded top view,
b is an exploded sectional view. Figure 3 shows n channel.
Figure 4, which symbolically shows SITh, is a lumped constant equivalent circuit when SITh is enclosed in a package. FIG. 5 is an exploded top view (a) and an exploded cross-sectional view (b) of an embodiment of a semiconductor device according to the present invention in which all electrode leads are made into plate shapes to reduce an inductance component. FIG. 6 is an exploded cross-sectional view of another embodiment of the present invention in which a metal base for fixing a semiconductor device and dissipating heat is electrically insulated from a conductor on which a semiconductor device substrate is mounted and serving as an electrode. FIG. 7 is an exploded sectional view of another embodiment of the present invention in which the directions of extraction are not the same as in FIG. 6, but are taken out at an angle of 90°. FIG. 8 shows still another embodiment configured to facilitate circuit arrangement when the carrier injection main electrode is used as a common potential terminal. FIG. 9 shows another embodiment of the present invention in which the carrier injection main electrode of the semiconductor device is directly connected to the conductor plate lead via a molybdenum plate.
FIG. 10 is a perspective view showing a specific example of the shape of the embodiment shown in FIG. FIG. 11 shows a circuit for examining the characteristics of the semiconductor device of the present invention, and FIG. 12a shows switching waveforms when the lead wires of capacitors C D and C g are made to have large inductance in the circuit shown in FIG. 11. Figure b shows the switching waveform when the lead wires of the capacitors C D and C g are configured to effectively reduce the inductance. FIG. 13 shows the switching waveform when a large current is switched by the circuit of FIG. 11 using the semiconductor device of the present invention in which a BSIT is inserted into the package of the embodiment of FIG. 10. be. 1, 11a, 11b, 21a, 21b, 21j
...Semiconductor device substrate, 2a, 2b, 22a,
22b, 22j, 34...Molybdenum plate, 3a,
3b... Metal conductor block, 4a, 4b... Flange, 5a, 5b... Welding plate, 6... Ceramic case, 7... Sealing pipe/control electrode extraction hole, 8... Control lead electrode, 12... ...Metal base, 13a, 13b...Electrode lead, 14...Ceramic case, 15a, 15b, 26a, 26
b... Bonding wire (or ribbon lead), 23... Conductor base, 24, 25... Conductor plate lead, 27... Insulator case, 29... Insulating plate, 30... Metal base, 31... Copper, etc. 32... Metal plate, 33, 36, 37... Insulator, 35... Conductor plate lead, 38... Seal plate.

Claims (1)

【特許請求の範囲】 1 第一および第二主表面を有し、ほぼ矩形状を
なす三端子半導体デバイス基板を封入し、互いに
絶縁体によつて電気的に分離された第一、第二、
第三のリード電極導体を有する半導体装置におい
て、前記第一のリード電極導体は前記半導体デバ
イス基板の前記第二主表面に接続され、少なくと
も前記半導体デバイス基板の全部を載置するのに
十分な幅と長さを有する板状のものであり、前記
第二および第三のリード電極導体は、前記矩形状
をなす半導体デバイス基板の前記第一主表面の前
記矩形の長辺部上に構成された電極部に対し、ボ
ンデイングワイヤ、リボンリード、またはモリブ
デン板を介して接続された板状のものであり、そ
れら第二および第三のリード電極導体の少なくと
も一方の幅の寸法を第二および第三のリード電極
導体の間隔より広くしたことを特徴とする半導体
装置。 2 前記第二および第三のリード電極導体の幅の
寸法を前記半導体デバイス基板の前記矩形の長辺
の長さとほぼ同じか大きくしたことを特徴とする
特許請求の範囲第1項記載の半導体装置。 3 前記ほぼ矩形状をなす三端子半導体デバイス
基板が、複数個の半導体デバイス基板を列状に配
置して成るものであり、前記第二および第三のリ
ード電極導体の幅の寸法を前記列状配置の複数個
の半導体デバイス基板の列方向の寸法よりも大き
くしたことを特徴とする特許請求の範囲第1項記
載の半導体装置。
[Scope of Claims] 1. A first, a second, and a semiconductor device having first and second main surfaces, encapsulating a substantially rectangular three-terminal semiconductor device substrate, and electrically separated from each other by an insulator.
In a semiconductor device having a third lead electrode conductor, the first lead electrode conductor is connected to the second main surface of the semiconductor device substrate, and has a width sufficient to place at least the entire semiconductor device substrate. and the second and third lead electrode conductors are formed on the long sides of the rectangle of the first main surface of the rectangular semiconductor device substrate. It is a plate-shaped thing connected to the electrode part via a bonding wire, a ribbon lead, or a molybdenum plate, and the width dimension of at least one of the second and third lead electrode conductors is the second and third lead electrode conductor. A semiconductor device characterized in that the spacing between the lead electrode conductors is wider than that of the lead electrode conductor. 2. The semiconductor device according to claim 1, wherein the width of the second and third lead electrode conductors is approximately the same as or larger than the length of the long side of the rectangle of the semiconductor device substrate. . 3. The substantially rectangular three-terminal semiconductor device substrate is formed by arranging a plurality of semiconductor device substrates in a row, and the width dimension of the second and third lead electrode conductors is set in the row shape. The semiconductor device according to claim 1, characterized in that the dimension in the column direction of the plurality of semiconductor device substrates arranged is larger than that of the plurality of semiconductor device substrates arranged.
JP57189983A 1982-07-23 1982-10-30 Semiconductor device Granted JPS5980945A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP57189983A JPS5980945A (en) 1982-10-30 1982-10-30 Semiconductor device
US06/516,543 US4692789A (en) 1982-07-23 1983-07-22 Semiconductor apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57189983A JPS5980945A (en) 1982-10-30 1982-10-30 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS5980945A JPS5980945A (en) 1984-05-10
JPS643061B2 true JPS643061B2 (en) 1989-01-19

Family

ID=16250434

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57189983A Granted JPS5980945A (en) 1982-07-23 1982-10-30 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5980945A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2559153Y2 (en) * 1991-12-12 1998-01-14 内山工業株式会社 Head cover gasket

Also Published As

Publication number Publication date
JPS5980945A (en) 1984-05-10

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