JPS643044Y2 - - Google Patents
Info
- Publication number
- JPS643044Y2 JPS643044Y2 JP2100181U JP2100181U JPS643044Y2 JP S643044 Y2 JPS643044 Y2 JP S643044Y2 JP 2100181 U JP2100181 U JP 2100181U JP 2100181 U JP2100181 U JP 2100181U JP S643044 Y2 JPS643044 Y2 JP S643044Y2
- Authority
- JP
- Japan
- Prior art keywords
- filter circuit
- output
- resistor
- load
- diodes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000003990 capacitor Substances 0.000 claims description 8
- 238000010586 diagram Methods 0.000 description 5
- 230000004043 responsiveness Effects 0.000 description 3
- 101150006573 PAN1 gene Proteins 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 239000002131 composite material Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000005303 weighing Methods 0.000 description 1
Landscapes
- Measurement Of Current Or Voltage (AREA)
Description
【考案の詳細な説明】 この考案は電子天びんに関する。[Detailed explanation of the idea] This invention relates to electronic balances.
一般に、電子天びんにおいて振動、電気的ノイ
ズなどの外乱による表示のチラツキをなくすため
に荷重−電気変換装置のアナログ信号はフイルタ
回路にて高周波成分をカツトしたのち演算、表示
等の信号処理回路部へ送られる。 Generally, in electronic balances, in order to eliminate display flickering due to disturbances such as vibration and electrical noise, the analog signal from the load-to-electricity converter is filtered to remove high frequency components before being sent to the signal processing circuit for calculation, display, etc. Sent.
このフイルタ回路として従来の電子天びんでは
第２図，に示すようなローパスフイルタ回路
が用いられていたが、天びんが安定するまでの時
間、すなわち天びんの応答性が悪くなる欠点があ
つた。すなわち、第３図に示すような荷重変化
があつた場合、荷重−電気変換装置の出力（フイ
ルタ入力電圧）は通常第３図のＡように推移す
るが、従来例として第２図に示したローパスフイ
ルタの時定数を大きく設定すると第３図の曲線
B2に示すように出力電圧が平衡状態に達して安
定するまでに長時間を要する欠点があり、これに
対し時定数を小さく設定すると（第３図の曲線
B1）平衡状態に達したのちも外乱等により表示
がちらつく欠点が生じた。 A low-pass filter circuit as shown in FIG. 2 has been used in conventional electronic balances as this filter circuit, but it has the disadvantage that the time it takes for the balance to stabilize, that is, the responsiveness of the balance deteriorates. In other words, when there is a load change as shown in Figure 3, the output of the load-to-electricity converter (filter input voltage) normally changes as shown in Figure 3 A, but as a conventional example, it changes as shown in Figure 2. When the time constant of the low-pass filter is set large, the curve shown in Figure 3
As shown in B 2 , there is a drawback that it takes a long time for the output voltage to reach an equilibrium state and become stable.In contrast, if the time constant is set small (the curve in Figure 3
B1 ) There was a drawback that the display flickered due to disturbances even after reaching an equilibrium state.
この考案の目的は上記従来の欠点を解消して、
外乱に対する安定度が優れ、かつ出力の応答性が
よい電子天びんを提供することにある。 The purpose of this invention is to eliminate the above-mentioned conventional drawbacks,
An object of the present invention is to provide an electronic balance that has excellent stability against disturbances and good output responsiveness.
この考案の電子天びんは、荷重−電気変換装置
の出力をコンデンサと抵抗からなるローパスフイ
ルタ回路を経て演算、表示等の信号処理回路部へ
導入する電子天びんにおいて、上記フイルタ回路
の抵抗の両端に互いに逆極性の一対のダイオード
を並列接続したことを特徴としている。 The electronic balance of this invention introduces the output of a load-to-electricity converter through a low-pass filter circuit consisting of a capacitor and a resistor to a signal processing circuit for calculation, display, etc. It is characterized by a pair of diodes of opposite polarity connected in parallel.
以下、この考案の実施例を図面に基づき説明す
る。 Hereinafter, embodiments of this invention will be described based on the drawings.
この実施例の構成を第１図に示す。荷重−電気
変換装置２は天びんの皿１上に載せられた試料Ｓ
の荷重をアナログ電気信号に変換する。このアナ
ログ電気信号はフイルタ回路３に導入されたのち
Ａ／Ｄ変換器４に入力される。Ａ／Ｄ変換器４の
出力は表示器５などに導入される。荷重−電気変
換装置２はロードセルや電磁力平衡方式などによ
つて構成される。 The configuration of this embodiment is shown in FIG. A load-electricity converter 2 is used to convert a sample S placed on a balance pan 1.
Converts the load into an analog electrical signal. This analog electrical signal is introduced into a filter circuit 3 and then input into an A/D converter 4. The output of the A/D converter 4 is introduced to a display 5 or the like. The load-electrical conversion device 2 is configured by a load cell, an electromagnetic force balance method, or the like.
フイルタ回路３は第４図のように構成され
る。すなわち、コンデンサC4、抵抗R4からなる
C4R4ローパスフイルタ回路においてダイオード
D1，D2が互いに逆極性で抵抗R4に並列接続され
ている。 The filter circuit 3 is constructed as shown in FIG. That is, it consists of capacitor C 4 and resistor R 4
C 4 R 4 Diode in low pass filter circuit
D 1 and D 2 are connected in parallel to resistor R 4 with opposite polarities.
上記実施例の作用を説明する。 The operation of the above embodiment will be explained.
天びんの皿１上に試料Ｓを載せない時にはフイ
ルタ回路３の入力端子電圧と出力端子電圧の差は
ないので、ダイオードD1，D2の抵抗成分は非常
に大きくなり、従つて時定数はほぼR4×C4に等
しく大きい値になつている。試料Ｓが皿１上に載
せられると、荷重−電気変換装置２により試料Ｓ
の荷重に対応した出力がフイルタ回路３に導入さ
れるので、上記入力端子電圧と上記出力端子電圧
との差が生じダイオードD1，D2の両端に加わる
電圧が増加する。その結果ダイオードの抵抗成分
が小さくなり時定数が小さくなる。従つて、速や
かにコンデンサC4の充電が行われ、皿１上に試
料Ｓが載せられた直後のフイルタ回路３出力が安
定する。次に、荷重−電気変換装置２の出力が安
定し始めると、フイルタ回路３の入力端子電圧と
出力端子電圧の差が減少し、再びダイオードD1，
D2の抵抗成分は増加する。すなわち、時定数が
ほぼR4×C4の大きい値に戻り、出力の安定性が
よくなる。以上のようにフイルタ入力端子電圧と
出力端子電圧の差Ｖに対するダイオードD1，D2
の抵抗と抵抗R4との合成抵抗値は第６図のよう
に変わる。 When the sample S is not placed on the balance pan 1, there is no difference between the input terminal voltage and the output terminal voltage of the filter circuit 3, so the resistance components of the diodes D 1 and D 2 become very large, and therefore the time constant is approximately It has become a large value equal to R 4 × C 4 . When the sample S is placed on the plate 1, the load-electricity converter 2
Since an output corresponding to the load is introduced into the filter circuit 3, a difference occurs between the input terminal voltage and the output terminal voltage, and the voltage applied across the diodes D 1 and D 2 increases. As a result, the resistance component of the diode becomes smaller and the time constant becomes smaller. Therefore, the capacitor C4 is quickly charged, and the output of the filter circuit 3 becomes stable immediately after the sample S is placed on the plate 1. Next, when the output of the load-to-electrical converter 2 begins to stabilize, the difference between the input terminal voltage and the output terminal voltage of the filter circuit 3 decreases, and the diode D 1 ,
The resistance component of D 2 increases. That is, the time constant returns to a large value of approximately R 4 ×C 4 , improving the stability of the output. As described above, the diodes D 1 and D 2 for the difference V between the filter input terminal voltage and output terminal voltage
The combined resistance value of the resistance R4 and the resistance R4 changes as shown in FIG.
また、上記実施例のフイルタ出力電圧特性は第
３図のＣに示すように秤量開始直後から安定し
て、かつ所定の出力電圧レベルに速やかに達す
る。 Further, the filter output voltage characteristic of the above embodiment is stable immediately after the start of weighing, and quickly reaches a predetermined output voltage level, as shown in C of FIG.
フイルタ回路３は第４図，に示す構成によ
つても実施することができる。 The filter circuit 3 can also be implemented with the configuration shown in FIG.
第４図では、抵抗R5とコンデンサC5からな
るC5R5フイルタと抵抗R6とコンデンサC6からな
るC6R6フイルタからなる二段形フイルタ回路に
おいて、ダイオードD3，D4が互いに逆極性で抵
抗R7に並列接続されている。 In Figure 4, in a two-stage filter circuit consisting of a C 5 R 5 filter consisting of a resistor R 5 and a capacitor C 5 , and a C 6 R 6 filter consisting of a resistor R 6 and a capacitor C 6 , diodes D 3 and D 4 are They are connected in parallel to resistor R 7 with opposite polarity.
第４図では、抵抗R7とコンデンサC7からな
るC7R7フイルタと抵抗R8とコンデンサC8からな
るC8R8フイルタからなる二段形フイルタ回路に
おいて、ダイオードD5，D6が抵抗R7に互いに逆
極性で並列接続され、かつダイオードD7，D8が
抵抗R8に互いに逆極性で並列接続され、さらに
ダイオードD5，D6とダイオードD7，D8は直並列
接続されている。 In Figure 4, in a two-stage filter circuit consisting of a C 7 R 7 filter consisting of a resistor R 7 and a capacitor C 7 , and a C 8 R 8 filter consisting of a resistor R 8 and a capacitor C 8 , diodes D 5 and D 6 are They are connected in parallel to resistor R 7 with opposite polarities, and diodes D 7 and D 8 are connected in parallel to resistor R 8 with opposite polarities, and diodes D 5 and D 6 and diodes D 7 and D 8 are connected in series and parallel. has been done.
以上の第４図，のフイルタ回路を用いて実
施した場合にも上記実施例と同様のフイルタ出力
特性を得ることができる。 Even when the filter circuit shown in FIG. 4 is used, the same filter output characteristics as in the above embodiment can be obtained.
この考案によれば、従来回路に互に逆極性の一
対のダイオードを付加するだけで、表示のラチツ
キがなく出力の応答性に優れた電子天びんを、安
価に得ることができる。 According to this invention, an electronic balance with no display flickering and excellent output responsiveness can be obtained at low cost by simply adding a pair of diodes of opposite polarity to a conventional circuit.
第１図はこの考案の実施例を示す回路ブロツク
図である。第２図は従来例のフイルタ回路を示す
回路図である。第３図は上記実施例及び上記従来
例の出力特性を説明するための作用説明図であ
る。第４図は上記実施例のフイルタ回路３を示す
回路図である。第５図は上記実施例の作用を説明
するための合成抵抗値変化図である。
２……荷重−電気変換装置、３……フイルタ回
路、４……Ａ／Ｄ変換器。
FIG. 1 is a circuit block diagram showing an embodiment of this invention. FIG. 2 is a circuit diagram showing a conventional filter circuit. FIG. 3 is an operational explanatory diagram for explaining the output characteristics of the above embodiment and the above conventional example. FIG. 4 is a circuit diagram showing the filter circuit 3 of the above embodiment. FIG. 5 is a composite resistance value change diagram for explaining the operation of the above embodiment. 2... Load-electrical conversion device, 3... Filter circuit, 4... A/D converter.
Claims (1)
からなるローパスフイルタ回路を経て演算、表示
等の信号処理回路部へ導入する電子天びんにおい
て、上記フイルタ回路の抵抗の両端に互いに逆極
性の一対のダイオードを並列接続したことを特徴
とする電子天びん。 In an electronic balance in which the output of a load-to-electricity converter is introduced into a signal processing circuit for calculation, display, etc. through a low-pass filter circuit consisting of a capacitor and a resistor, a pair of diodes with opposite polarities are connected to both ends of the resistor of the filter circuit. An electronic balance characterized by parallel connection.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2100181U JPS643044Y2 (en) | 1981-02-16 | 1981-02-16 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2100181U JPS643044Y2 (en) | 1981-02-16 | 1981-02-16 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57134640U JPS57134640U (en) | 1982-08-21 |
| JPS643044Y2 true JPS643044Y2 (en) | 1989-01-26 |
Family
ID=29818896
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2100181U Expired JPS643044Y2 (en) | 1981-02-16 | 1981-02-16 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS643044Y2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60114723A (en) * | 1983-11-26 | 1985-06-21 | Anritsu Corp | Measuring apparatus |
| JPS60209120A (en) * | 1984-03-31 | 1985-10-21 | Anritsu Corp | Measuring device |
-
1981
- 1981-02-16 JP JP2100181U patent/JPS643044Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57134640U (en) | 1982-08-21 |
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