JPS6429827U - - Google Patents
Info
- Publication number
- JPS6429827U JPS6429827U JP12368687U JP12368687U JPS6429827U JP S6429827 U JPS6429827 U JP S6429827U JP 12368687 U JP12368687 U JP 12368687U JP 12368687 U JP12368687 U JP 12368687U JP S6429827 U JPS6429827 U JP S6429827U
- Authority
- JP
- Japan
- Prior art keywords
- leads
- die pad
- semiconductor element
- semiconductor device
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 12
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Wire Bonding (AREA)
- Die Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
第1図乃至第4図において、本考案の実施例が
示され、第1図は半導体装置の斜視図、第2図は
半導体装置の断面図、第3図は他の実施例を示す
半導体装置の斜視図、第4図は他の実施例を示す
半導体装置の断面図であり、第5図及び第6図に
おいて従来例が示され、第5図は半導体装置の斜
視図、第6図は半導体装置の断面図である。
2……ダイパツド、3……リード、4……半導
体素子、4a……ワイヤボンデイング面。
1 to 4, an embodiment of the present invention is shown, FIG. 1 is a perspective view of a semiconductor device, FIG. 2 is a sectional view of the semiconductor device, and FIG. 3 is a semiconductor device showing another embodiment. FIG. 4 is a cross-sectional view of a semiconductor device showing another embodiment, and FIGS. 5 and 6 show a conventional example. FIG. 5 is a perspective view of the semiconductor device, and FIG. FIG. 2 is a cross-sectional view of a semiconductor device. 2... Die pad, 3... Lead, 4... Semiconductor element, 4a... Wire bonding surface.
Claims (1)
ツドに近接して複数のリードを有し、前記半導体
素子と前記リードがワイヤボンデイングされた半
導体装置において、 前記ダイパツドと前記リードは同一平面に配置
され、前記リードの先端が前記半導体素子のワイ
ヤボンデイング面方向に屈曲されたことを特徴と
する半導体装置。[Claims for Utility Model Registration] A semiconductor device having a die pad on which a semiconductor element is mounted and a plurality of leads adjacent to the die pad, the semiconductor element and the leads being wire bonded, wherein the die pad and the leads are A semiconductor device, characterized in that the leads are arranged on the same plane, and the tips of the leads are bent in the direction of the wire bonding surface of the semiconductor element.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12368687U JPS6429827U (en) | 1987-08-12 | 1987-08-12 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12368687U JPS6429827U (en) | 1987-08-12 | 1987-08-12 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6429827U true JPS6429827U (en) | 1989-02-22 |
Family
ID=31372764
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12368687U Pending JPS6429827U (en) | 1987-08-12 | 1987-08-12 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6429827U (en) |
-
1987
- 1987-08-12 JP JP12368687U patent/JPS6429827U/ja active Pending