JPS6429085A - Input/output controller - Google Patents

Input/output controller

Info

Publication number
JPS6429085A
JPS6429085A JP62184832A JP18483287A JPS6429085A JP S6429085 A JPS6429085 A JP S6429085A JP 62184832 A JP62184832 A JP 62184832A JP 18483287 A JP18483287 A JP 18483287A JP S6429085 A JPS6429085 A JP S6429085A
Authority
JP
Japan
Prior art keywords
processor
terminals
input
switch
processors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62184832A
Other languages
Japanese (ja)
Inventor
Takafumi Saito
Yoshimitsu Honma
Akira Hayama
Kiyoshi Ishikawa
Takaharu Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Nippon Telegraph and Telephone Corp
Original Assignee
Toshiba Corp
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Nippon Telegraph and Telephone Corp filed Critical Toshiba Corp
Priority to JP62184832A priority Critical patent/JPS6429085A/en
Publication of JPS6429085A publication Critical patent/JPS6429085A/en
Pending legal-status Critical Current

Links

Landscapes

  • Multi Processors (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
  • Exchange Systems With Centralized Control (AREA)
  • Hardware Redundancy (AREA)

Abstract

PURPOSE:To make respective terminals access an arbitrary processor without through other processors by providing a switch to connect an arbitrary processor independently to respective terminals, and controlling this switch in accordance with an instruction from each terminal. CONSTITUTION:A common memory 11 to execute input/output control is provided as a switch means between the processors 1, 2 and terminals 3a-3n. The respectively terminals 3a-3n, even in case of inputting/outputting information to/from the reserve processor 2, can execute the intputting/outputting to/ from the common memory 11 without through the processor 1 in current use.
JP62184832A 1987-07-24 1987-07-24 Input/output controller Pending JPS6429085A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62184832A JPS6429085A (en) 1987-07-24 1987-07-24 Input/output controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62184832A JPS6429085A (en) 1987-07-24 1987-07-24 Input/output controller

Publications (1)

Publication Number Publication Date
JPS6429085A true JPS6429085A (en) 1989-01-31

Family

ID=16160085

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62184832A Pending JPS6429085A (en) 1987-07-24 1987-07-24 Input/output controller

Country Status (1)

Country Link
JP (1) JPS6429085A (en)

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