JPS6427092A - Output circuit - Google Patents

Abstract

PURPOSE:To decrease noise based on the sudden change of a charging and discharging current by minimizing influence to output characteristics and restricting the variation in time of the charging and discharging current and a maximum value at the time of the output change of an IC memory. CONSTITUTION:After an output data signal D, an output control signal OE and the inverse of OE are passed through a NOR gate 1 and a NAND gate 2 respectively, a signals O1 and O3 inverted at inverters 5 and 6 are inputted into the gates of transistor TRP1 and N3 respectively. Signals O2 and O4, which are obtained by passing the output signal of the NOR gate 1 and the NAND gate 2 through a leading delay circuit consisting of a delay circuit 3 and a NAND gate 7 and a trailing delay circuit consisting of a delay circuit 4 and a NOR gate 8, are inputted into the gates of TRP2 and N4 respectively. Thus, an output signal OUT and a current IC at the time of output charging and discharging go to a waveform shown by full lines in which the change in time and the maximum value of the current, compared with broken line characteristics when TRP1, P2, TRN3 and N4 turn on/off respective at the same time.