JPS6425358A - Phase pull-in control circuit - Google Patents

Phase pull-in control circuit

Info

Publication number
JPS6425358A
JPS6425358A JP18275487A JP18275487A JPS6425358A JP S6425358 A JPS6425358 A JP S6425358A JP 18275487 A JP18275487 A JP 18275487A JP 18275487 A JP18275487 A JP 18275487A JP S6425358 A JPS6425358 A JP S6425358A
Authority
JP
Japan
Prior art keywords
control circuit
circuit
pull
updated
timing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18275487A
Other languages
Japanese (ja)
Inventor
Yoshiaki Okada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP18275487A priority Critical patent/JPS6425358A/en
Publication of JPS6425358A publication Critical patent/JPS6425358A/en
Pending legal-status Critical Current

Links

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  • Signal Processing For Digital Recording And Reproducing (AREA)

Abstract

PURPOSE:To prevent the re-generation of an error and to shorten an access time by remaining a pull-in timing as information data on a recording medium while it is updated by the pull-in timing successful in the reading. CONSTITUTION:The circuit is composed of a register circuit 1, a phase locked loop oscillator control circuit 2, a system control circuit 3, a read write circuit 8 and a memory medium 9. The phase locked loop oscillator control circuit 2 generates a phase locked loop oscillator control timing by the medium defect information sent from the system control circuit 3, sends it to a read write control circuit 8, a pull-in error occurs newly, then, the medium defect information is updated, sent to the system control circuit 3 and written to the register circuit 1. When the medium defect information is updated and the action of the disk device is stopped, the contents of the register circuit 1 are written into one area. Thus, the re-generation of the pull-in error can be prevented and the access time can be shortened.
JP18275487A 1987-07-21 1987-07-21 Phase pull-in control circuit Pending JPS6425358A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18275487A JPS6425358A (en) 1987-07-21 1987-07-21 Phase pull-in control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18275487A JPS6425358A (en) 1987-07-21 1987-07-21 Phase pull-in control circuit

Publications (1)

Publication Number Publication Date
JPS6425358A true JPS6425358A (en) 1989-01-27

Family

ID=16123852

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18275487A Pending JPS6425358A (en) 1987-07-21 1987-07-21 Phase pull-in control circuit

Country Status (1)

Country Link
JP (1) JPS6425358A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006034540A (en) * 2004-07-26 2006-02-09 Shiseido Co Ltd Beauty treatment method and beauty equipment for the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006034540A (en) * 2004-07-26 2006-02-09 Shiseido Co Ltd Beauty treatment method and beauty equipment for the same

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