JPS6424623A - Pulse delay circuit - Google Patents
Pulse delay circuitInfo
- Publication number
- JPS6424623A JPS6424623A JP62180116A JP18011687A JPS6424623A JP S6424623 A JPS6424623 A JP S6424623A JP 62180116 A JP62180116 A JP 62180116A JP 18011687 A JP18011687 A JP 18011687A JP S6424623 A JPS6424623 A JP S6424623A
- Authority
- JP
- Japan
- Prior art keywords
- monostable multivibrator
- horizontal synchronizing
- multivibrator circuit
- synchronizing signal
- output pulse
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Synchronizing For Television (AREA)
- Pulse Circuits (AREA)
Abstract
PURPOSE:To display a video signal on a cathode ray tube faceplate without hindrance even if missing or disturbance of a horizontal synchronizing signal exists by using a monostable multivibrator circuit triggered by a horizontal driving pulse having always constant delay and an operational amplifier even if a horizontal synchronizing (frequency) varies. CONSTITUTION:The pulse width of an output pulse (g) of the 3rd monostable vibrator circuit 7 and that of an output pulse (b) of the 1st monostable multivibrator circuit 1 have a constant ratio (T1/T1). Moreover, the output pulse of a 3rd monostable multivibrator circuit 7 is fed to 1st and 2nd monostable multivibrator circuits 1, 2 as a delay control variable from an operational amplifier 8 to retard a horizontal synchronizing signal (a) without losing the relation of the delay ratio (T1/T2). If the period T of the horizontal synchronizing signal (a) is changed, the integration voltage of the 3rd monostable multivibrator circuit 7 is changed and the operational amplifier 8 is operated so as to make the voltage equal to a voltage (e) of an inverting input, and then the ratio (T1/T2) is kept constant. Then the output pulse C of the 2nd monostable multivibrator circuit 2 has a constant delay ratio (T1+T2/T) at all times with respect to horizontal synchronizing signal (a).
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62180116A JPH077908B2 (en) | 1987-07-21 | 1987-07-21 | Pulse delay circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62180116A JPH077908B2 (en) | 1987-07-21 | 1987-07-21 | Pulse delay circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6424623A true JPS6424623A (en) | 1989-01-26 |
JPH077908B2 JPH077908B2 (en) | 1995-01-30 |
Family
ID=16077698
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62180116A Expired - Fee Related JPH077908B2 (en) | 1987-07-21 | 1987-07-21 | Pulse delay circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH077908B2 (en) |
-
1987
- 1987-07-21 JP JP62180116A patent/JPH077908B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JPH077908B2 (en) | 1995-01-30 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
LAPS | Cancellation because of no payment of annual fees |