JPS6424542A - Timing synchronizing circuit for modem - Google Patents

Timing synchronizing circuit for modem

Info

Publication number
JPS6424542A
JPS6424542A JP62180676A JP18067687A JPS6424542A JP S6424542 A JPS6424542 A JP S6424542A JP 62180676 A JP62180676 A JP 62180676A JP 18067687 A JP18067687 A JP 18067687A JP S6424542 A JPS6424542 A JP S6424542A
Authority
JP
Japan
Prior art keywords
reception timing
timing phase
phase
shift
shifted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62180676A
Other languages
Japanese (ja)
Inventor
Fuyuki Abe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP62180676A priority Critical patent/JPS6424542A/en
Publication of JPS6424542A publication Critical patent/JPS6424542A/en
Pending legal-status Critical Current

Links

Landscapes

  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To vary a reception timing phase to a transmission timing phase within a training period by deciding the direction and quantity of a shift in the reception timing phase and shifting the phase. CONSTITUTION:A signal with a transmission timing waveform is sampled at a frequency 6N (N: positive integer) times as large as a modulation speed according to the reception timing phase to discriminate whether the reception timing phase leads or lags from 1st and (4N)th comparison in one rotation of the reception timing and whether the shift quantity of the reception timing is larger or smaller than 90 deg. from the comparison result between the absolute values of (2N)th and (3N)th sampled values. Then when the shift quantity is <=90 deg., the reception timing phase is shifted in the opposite direction from the shift until 1st and (4N)th sampled values become equal to each other and when >90 deg., the reception timing phase is shifted in the same direction with the shift until the 1st and (4N)th sampled values become equal to each other. Consequently, the reception timing phase can be shifted by invariably <=90 deg. to the transmission timing phase.
JP62180676A 1987-07-20 1987-07-20 Timing synchronizing circuit for modem Pending JPS6424542A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62180676A JPS6424542A (en) 1987-07-20 1987-07-20 Timing synchronizing circuit for modem

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62180676A JPS6424542A (en) 1987-07-20 1987-07-20 Timing synchronizing circuit for modem

Publications (1)

Publication Number Publication Date
JPS6424542A true JPS6424542A (en) 1989-01-26

Family

ID=16087358

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62180676A Pending JPS6424542A (en) 1987-07-20 1987-07-20 Timing synchronizing circuit for modem

Country Status (1)

Country Link
JP (1) JPS6424542A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03253117A (en) * 1990-03-02 1991-11-12 Nec Corp Timing extraction circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03253117A (en) * 1990-03-02 1991-11-12 Nec Corp Timing extraction circuit

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