JPS6423548A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPS6423548A
JPS6423548A JP17890287A JP17890287A JPS6423548A JP S6423548 A JPS6423548 A JP S6423548A JP 17890287 A JP17890287 A JP 17890287A JP 17890287 A JP17890287 A JP 17890287A JP S6423548 A JPS6423548 A JP S6423548A
Authority
JP
Japan
Prior art keywords
mode
test
written
state
memory element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17890287A
Other languages
Japanese (ja)
Inventor
Manabu Shibata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP17890287A priority Critical patent/JPS6423548A/en
Publication of JPS6423548A publication Critical patent/JPS6423548A/en
Pending legal-status Critical Current

Links

Landscapes

  • Tests Of Electronic Circuits (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Dram (AREA)

Abstract

PURPOSE:To easily detect a breakdown or to easily diagnose an operation by a method wherein a nonvolatile memory element which is written by a level of a power-supply voltage is installed and a changeover between a test mode and a normal mode is set by its memory state. CONSTITUTION:A mode changeover circuit 3 and a setting circuit 4 are constituted in such a way that they set a test mode in an erased state of a memory element M and that they set a normal mode in a written state. In a semiconductor integrated circuit device 10 the test mode is automatically set in an initial state that the memory element M is not written. Accordingly, it is possible to efficiently execute a test to detect a breakdown, to diagnose an operation or the like in this state. If this test is completed, only a product judged to be good is selected; a prescribed write voltage is impressed on power-supply terminals P1, P2; the memory element M is written; the test mode is released and the normal operation mode can be set. By this setup, a changeover between the normal mode and the test mode can be set without increasing the number of terminals; it is possible to detect the breakdown or to diagnose the operation easily.
JP17890287A 1987-07-20 1987-07-20 Semiconductor integrated circuit device Pending JPS6423548A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17890287A JPS6423548A (en) 1987-07-20 1987-07-20 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17890287A JPS6423548A (en) 1987-07-20 1987-07-20 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPS6423548A true JPS6423548A (en) 1989-01-26

Family

ID=16056686

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17890287A Pending JPS6423548A (en) 1987-07-20 1987-07-20 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS6423548A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0580130A (en) * 1991-09-20 1993-04-02 Nec Corp Semiconductor integrated circuit
US5719625A (en) * 1990-05-25 1998-02-17 Asahi Kogaku Kogyo Kabushiki Kaisha Device for controlling imaging device
US6064627A (en) * 1996-09-26 2000-05-16 Mitsubishi Denki Kabushiki Kaisha Synchronous semiconductor memory device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5719625A (en) * 1990-05-25 1998-02-17 Asahi Kogaku Kogyo Kabushiki Kaisha Device for controlling imaging device
JPH0580130A (en) * 1991-09-20 1993-04-02 Nec Corp Semiconductor integrated circuit
US6064627A (en) * 1996-09-26 2000-05-16 Mitsubishi Denki Kabushiki Kaisha Synchronous semiconductor memory device

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