JPS6423285A - Frame buffer apparatus - Google Patents

Frame buffer apparatus

Info

Publication number
JPS6423285A
JPS6423285A JP62180606A JP18060687A JPS6423285A JP S6423285 A JPS6423285 A JP S6423285A JP 62180606 A JP62180606 A JP 62180606A JP 18060687 A JP18060687 A JP 18060687A JP S6423285 A JPS6423285 A JP S6423285A
Authority
JP
Japan
Prior art keywords
data
memory
frame buffer
ram
speed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62180606A
Other languages
Japanese (ja)
Inventor
Koichi Tanigawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to JP62180606A priority Critical patent/JPS6423285A/en
Publication of JPS6423285A publication Critical patent/JPS6423285A/en
Pending legal-status Critical Current

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  • Dram (AREA)

Abstract

PURPOSE: To facilitate high-speed drawing on a CRT and high-speed erasure at a RAM part by using a memory which can be accessed in series and at random for a frame buffer memory of an image processor, etc. CONSTITUTION: Image data stored in the frame buffer 4 are written to a RAM 5 on the memory 4 by an address controller 2. This stored data are read out by a frame buffer timing control 3 during the horizontal blanking of a horizontal synchronizing signal and transferred to a serial access memory(SAM) 6 by one horizontal line (256 bits) at a time. Then the data are outputted, pixel by pixel, through a serial I/O port 7 and displayed on the CRT. To erase the memory 4, on the other hand, erasure data are sent, bit by bit, to a port 7 and once data of one horizontal line are stored in the SAM 6, they are transferred to the RAM 5 at a time, thus erasing one horizontal line. This method enables a high-speed display of data and high-speed erasure of the RAM.
JP62180606A 1987-07-20 1987-07-20 Frame buffer apparatus Pending JPS6423285A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62180606A JPS6423285A (en) 1987-07-20 1987-07-20 Frame buffer apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62180606A JPS6423285A (en) 1987-07-20 1987-07-20 Frame buffer apparatus

Publications (1)

Publication Number Publication Date
JPS6423285A true JPS6423285A (en) 1989-01-25

Family

ID=16086189

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62180606A Pending JPS6423285A (en) 1987-07-20 1987-07-20 Frame buffer apparatus

Country Status (1)

Country Link
JP (1) JPS6423285A (en)

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