JPS642260B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention slices the distorted wave signal at a desired slice level according to the level of the distorted wave signal that has passed through a transmission system, other circuits, etc., and restores the original signal. This invention relates to a waveform shaping circuit for reproducing data.

Various waveform shaping circuits have been proposed in the past, but the basic one is to amplify the distorted wave signal to a predetermined level or higher, and then apply a certain level of bias to the amplified distorted wave signal. In many cases, the signal was sliced using a slice circuit or the like, and the slice signal was used to drive a bistable multivibrator or the like to reproduce a regular signal. In the waveform shaping circuit configured as above, the slice level is constant as described above, so the signal waveform after slicing will differ depending on whether the level of the distorted wave signal input to this circuit is high or low. It turns out.
As a result, the signal waveform reproduced by the waveform shaping circuit differs from the original signal waveform.

On the other hand, in television broadcasting and the like, from the viewpoint of effective use of radio waves, television multiplexed still image broadcasting has been proposed in which characters and still figures are multiplexed onto conventional television broadcast waves.

In this television multiplexed still image broadcasting, on the transmitting side, character signals and graphic signals are decomposed into horizontal lines and sent out using one horizontal line within a vertical blanking (VBL) period, and on the receiving side, This signal is extracted and stored in memory before being displayed on a picture tube. In this television multiplexed still picture broadcast, the signal waveform of the multiplexed signal is distorted when passing through the transmission system or the high frequency section and/or intermediate frequency amplification section of the receiver. Even if this distorted wave signal is sliced and waveform-shaped using the aforementioned waveform shaping circuit, etc., there will be a difference between the reproduced signal waveform and the original signal waveform. It was necessary to adjust.

The present invention has been made in view of the above points, and is a waveform shaping method that extracts a distorted wave signal that is distorted when the signal passes through a transmission system or various circuits, and shapes the waveform by slicing or the like. It is an object of the present invention to provide a waveform shaping circuit in which a slice level changes so that a desired signal can be reproduced even if the level of a distorted wave signal changes.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows, as an embodiment of the present invention, a synchronization detection circuit that inputs a distorted wave signal, a phase-locked loop circuit (PLL) that frequency-divides the output signal of a subcarrier (f _sc ) separation circuit, and the phase-locked loop circuit (PLL) described above. a gate signal forming means constituted by a gate signal generating circuit which forms a gate signal from the output signals of both circuits; A level control means comprising an input up/down counter and a digital-to-analog (D/A) conversion circuit whose output voltage is varied according to the output signal of the up/down counter, and an output signal of the level control means. A block diagram of a waveform shaping circuit including a slicing circuit for slicing a distorted wave signal at a corresponding slicing level is shown.

In FIG. 1, a distorted wave signal input from an input terminal _P1 is sent to a slice circuit 1 that slices this distorted wave signal at a desired slice level, a synchronization detection circuit 2 that detects a synchronization signal, and a subcarrier (f _sc ) signal and a subcarrier (f _sc ) separation circuit 3 for detecting the signal. The output of this f _sc separation circuit 3 is supplied to a gate signal generation circuit 5 via a PLL circuit 4 that multiplies this output signal f _sc by n/m (where m and n are arbitrary integers). It's like this. The gate signal generation circuit 5 is also supplied with an output signal from the synchronization detection circuit 2. Based on these signals, the gate signal generation circuit 5
In this method, a gate signal (control signal) for extracting a specific signal from a distorted wave signal is formed. The above configuration (excluding the slice circuit 1) is the gate signal forming means.

Next, the output signal of the slice circuit 1 is input to the up-down (U/D) counter 6 as an input signal for instructing whether to use the up-counter or the down-counter, and the output signal of the slice circuit 1 is inputted as the clock signal to the clock generation circuit 7. The output signal of is inputted via an AND gate 8. The other input terminal of the AND gate 8 is designed to AND the carry signal and the output signal of the clock generating circuit 7 to prevent the counter 6 from overflowing. Furthermore, the gate signal generation circuit 5
A gate signal is input to the U//D counter 6, and the U/D counter 6 is activated or deactivated by this gate signal. The output signal of the U/D counter 6 is converted into an analog signal by a digital-to-analog conversion circuit 9, and becomes a slice level signal. The above configuration is the level control means. The output signal of this level control means is input to the slice circuit 1.

The output signal of the slice circuit 1 is output from the output terminal _P0 .

The operation of the present invention having the above structure will be explained below with reference to FIGS. 2 and 3.

FIGS. 2 and 3 show signal waveform diagrams for explaining the operation of FIG. 1. In these figures, the horizontal axis represents time t, and the vertical axis represents the signal waveforms of the portions A to C in FIG. 1, respectively.

By the way, when the distorted wave signal supplied to the input terminal _P1 is applied to the slice circuit 1, the synchronization detection circuit 2, and the _fsc separation circuit 3, the synchronization signal of the synchronization detection circuit 2 and the _fsc separation circuit 3 are The separated f _sc signal
The PLL circuit 4 generates a specific signal portion of the digital superimposed signal from the n/mf _sc signal multiplied by n/m, that is, as shown in FIG.
It is a repeating signal like 10101010. ) is generated by the gate signal generation circuit 5. This gate signal then gates the U/D counter 6 into an active state. As a result, U/D counter 6
operates only while this gate signal is supplied. Further, as shown in FIG. 3, the U/D counter 6 is placed in the up-counter state during the clock run-in "1" period, and conversely, the U/D counter 6 is put in the down-counter state during the clock run-in "0" period. The period shall be set as .

By doing this, when the slice level decreases, the U/D counter 6 increases the period of up operation, the binary output of the counter 6 increases, and the D/A converter circuit 9 applies a high slice level to the slice circuit 1. It will be done. Then, the up-counter period and the down-counter period reach a point where their widths almost match, and the output of the D/A converter circuit 9, that is, the slice level, is maintained at this value.

Conversely, as the slice level becomes higher, the U/D counter 6 has more down-operation periods, and the binary output of the counter 6 becomes smaller. the result,
A low slice level is provided to the slice circuit 1 by the D/A conversion circuit 9. Therefore, from now on,
It will settle down when the widths of the up and down counter periods match. It operates as described above.

Further, by changing the clock frequency of the U/D counter 6 between the up counter period and the down counter period, an arbitrary duty output can be obtained, so that an arbitrary slice level can be selected.

As described above, according to the present invention, it is possible to detect a specific signal in a distorted wave signal and to vary the slice level based on this specific signal. This has the effect of being able to regenerate signals.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIGS. 2 and 3 are waveform diagrams for explaining the operation of the embodiment of FIG. 1. 1...Slice circuit, 2...Synchronization detection circuit, 3
... Subcarrier separation circuit, 4 ... Phase locked loop circuit, 5 ... Gate signal generation circuit, 6 ...
Up-down counter, 7...Clock generation circuit, 8...And gate, 9...Digital-to-analog conversion circuit.

Claims (1)

[Claims] 1. A slicing circuit for slicing a received signal at a predetermined slice level and shaping the waveform into a binary signal, and forming a gate signal indicating a specific signal period in the received signal output from this slicing circuit. a gate signal forming circuit; a clock generation circuit that outputs a clock having a higher frequency than the frequency of the specific signal; and a clock output from the clock generation circuit that outputs a clock during the gate signal period according to the polarity of the specific signal. or an up-down counter whose count value is controlled according to the duty ratio of the specific signal, and a digital-to-analog conversion of the count value output from the up-down counter, which is used as the slice level of the slice circuit. A waveform shaping circuit characterized by comprising a digital-to-analog conversion circuit for outputting data.