JPS6421451U - - Google Patents

Info

Publication number
JPS6421451U
JPS6421451U JP11499787U JP11499787U JPS6421451U JP S6421451 U JPS6421451 U JP S6421451U JP 11499787 U JP11499787 U JP 11499787U JP 11499787 U JP11499787 U JP 11499787U JP S6421451 U JPS6421451 U JP S6421451U
Authority
JP
Japan
Prior art keywords
circuit
arithmetic unit
clip code
sign bit
zero value
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11499787U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP11499787U priority Critical patent/JPS6421451U/ja
Publication of JPS6421451U publication Critical patent/JPS6421451U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本考案の一実施例を示すブロツク図、
第２図は一般的に使用されている浮動小数点数値
のフオーマツト、第３図は固定小数点演算器を使
用しない場合イと使用した場合ロの処理時間の比
較を示すタイムチヤートである。 １……固定小数点演算器、２……零値検出回路
、３……論理積回路、４，５……排他的論理和回
路、６……座標値データサインビツト、７……ク
リツプ枠データサインビツト、８……演算器出力
サインビツト、９……オーバフロー出力。 FIG. 1 is a block diagram showing an embodiment of the present invention.
FIG. 2 is a time chart showing a commonly used floating point value format, and FIG. 3 is a time chart showing a comparison of processing time between A when a fixed point arithmetic unit is not used and B when a fixed point arithmetic unit is used. 1... Fixed-point arithmetic unit, 2... Zero value detection circuit, 3... AND circuit, 4, 5... Exclusive OR circuit, 6... Coordinate value data sign bit, 7... Clip frame data sign Bit, 8...Arithmetic unit output sign bit, 9...Overflow output.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 浮動小数点座標値によつて動作しているクリツ
ピング回路において、固定小数点演算器と、零値
検出回路および論理回路から成るサインビツト補
正回路とを備えてクリツプコードを発生したこと
を特徴とするクリツプコード発生装置。 A clip code generator which generates a clip code by using a clipping circuit which operates based on floating point coordinate values and includes a fixed point arithmetic unit, a sign bit correction circuit consisting of a zero value detection circuit and a logic circuit. Device.
JP11499787U 1987-07-27 1987-07-27 Pending JPS6421451U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11499787U JPS6421451U (en) 1987-07-27 1987-07-27

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11499787U JPS6421451U (en) 1987-07-27 1987-07-27

Publications (1)

Publication Number Publication Date
JPS6421451U true JPS6421451U (en) 1989-02-02

Family

ID=31356251

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11499787U Pending JPS6421451U (en) 1987-07-27 1987-07-27

Country Status (1)

Country Link
JP (1) JPS6421451U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7189015B2 (en) 2004-06-08 2007-03-13 Fuji Photo Film Co., Ltd. Method for replenishing development replenisher in automatic developing machine for photosensitive lithographic printing plate precursor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7189015B2 (en) 2004-06-08 2007-03-13 Fuji Photo Film Co., Ltd. Method for replenishing development replenisher in automatic developing machine for photosensitive lithographic printing plate precursor

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