JPS63175247U - - Google Patents
Info
- Publication number
- JPS63175247U JPS63175247U JP6244088U JP6244088U JPS63175247U JP S63175247 U JPS63175247 U JP S63175247U JP 6244088 U JP6244088 U JP 6244088U JP 6244088 U JP6244088 U JP 6244088U JP S63175247 U JPS63175247 U JP S63175247U
- Authority
- JP
- Japan
- Prior art keywords
- scan
- address
- circuit
- logic
- polarity flag
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Test And Diagnosis Of Digital Computers (AREA)
Description
第１図が従来のスキヤンアウト機能についてブ
ロツク図で示した図、第２図が本考案の１実施例
を示した図である。
図において、１はデータ処理装置、２はスキヤ
ンアウト制御部、２１はスキヤンアウトアドレス
レジスタ、２２，２３は選択回路、２４は排他的
論理和回路、２５は論理積回路である。
FIG. 1 is a block diagram showing a conventional scan-out function, and FIG. 2 is a diagram showing an embodiment of the present invention. In the figure, 1 is a data processing device, 2 is a scan-out control section, 21 is a scan-out address register, 22 and 23 are selection circuits, 24 is an exclusive OR circuit, and 25 is an AND circuit.
Claims (1)
おいて、 スキヤンアウトアドレスの一部に、そのアドレ
スに対応する論理素子が正論理であるか、負論理
であるかを示す極性フラグを付加し、 スキヤンアウト機構の出力部において、前期ス
キヤンアウトアドレスに対応して、特定装置から
送られてくるスキヤンアウト結果と、前記スキヤ
ンアウトアドレス内の極性フラグとの排他的論理
和をとる回路と、 前記スキヤンアウトアドレスの装置指定アドレ
スをデコードして、選択された装置の電源がオフ
の状態の時は、該装置のスキヤンアウト結果を強
制的に論理“０”にする回路とを設けることを特
徴とするスキヤンアウト回路。[Scope of Claim for Utility Model Registration] In a data processing device having a scan-out function, a polarity flag indicating whether the logic element corresponding to the address is positive logic or negative logic is included in a part of the scan-out address. Additionally, in the output section of the scan-out mechanism, a circuit that performs an exclusive OR of the scan-out result sent from the specific device and the polarity flag in the scan-out address corresponding to the previous scan-out address; and a circuit that decodes the device specified address of the scan-out address and forcibly sets the scan-out result of the selected device to logic "0" when the power of the selected device is off. Features a scan-out circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6244088U JPH035953Y2 (en) | 1988-05-12 | 1988-05-12 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6244088U JPH035953Y2 (en) | 1988-05-12 | 1988-05-12 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63175247U true JPS63175247U (en) | 1988-11-14 |
| JPH035953Y2 JPH035953Y2 (en) | 1991-02-15 |
Family
ID=30896722
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6244088U Expired JPH035953Y2 (en) | 1988-05-12 | 1988-05-12 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH035953Y2 (en) |
-
1988
- 1988-05-12 JP JP6244088U patent/JPH035953Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPH035953Y2 (en) | 1991-02-15 |
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