JPS6420747U - - Google Patents
Info
- Publication number
- JPS6420747U JPS6420747U JP1987115425U JP11542587U JPS6420747U JP S6420747 U JPS6420747 U JP S6420747U JP 1987115425 U JP1987115425 U JP 1987115425U JP 11542587 U JP11542587 U JP 11542587U JP S6420747 U JPS6420747 U JP S6420747U
- Authority
- JP
- Japan
- Prior art keywords
- island
- leads
- lead frame
- branched
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000002184 metal Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05553—Shape in top view being rectangular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987115425U JPS6420747U (US20020167097A1-20021114-C00005.png) | 1987-07-27 | 1987-07-27 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987115425U JPS6420747U (US20020167097A1-20021114-C00005.png) | 1987-07-27 | 1987-07-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6420747U true JPS6420747U (US20020167097A1-20021114-C00005.png) | 1989-02-01 |
Family
ID=31357069
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987115425U Pending JPS6420747U (US20020167097A1-20021114-C00005.png) | 1987-07-27 | 1987-07-27 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6420747U (US20020167097A1-20021114-C00005.png) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5571030A (en) * | 1978-11-24 | 1980-05-28 | Hitachi Ltd | Mounting system for semiconductor device |
| JPS5878448A (ja) * | 1982-10-18 | 1983-05-12 | Hitachi Ltd | 集積回路 |
| JPS6119151A (ja) * | 1984-07-05 | 1986-01-28 | Nec Corp | 半導体装置 |
| JPS6211256A (ja) * | 1985-07-09 | 1987-01-20 | Fujitsu Ltd | 半導体集積回路装置 |
| JPS6214748B2 (US20020167097A1-20021114-C00005.png) * | 1984-02-08 | 1987-04-03 | Hitachi Ltd |
-
1987
- 1987-07-27 JP JP1987115425U patent/JPS6420747U/ja active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5571030A (en) * | 1978-11-24 | 1980-05-28 | Hitachi Ltd | Mounting system for semiconductor device |
| JPS5878448A (ja) * | 1982-10-18 | 1983-05-12 | Hitachi Ltd | 集積回路 |
| JPS6214748B2 (US20020167097A1-20021114-C00005.png) * | 1984-02-08 | 1987-04-03 | Hitachi Ltd | |
| JPS6119151A (ja) * | 1984-07-05 | 1986-01-28 | Nec Corp | 半導体装置 |
| JPS6211256A (ja) * | 1985-07-09 | 1987-01-20 | Fujitsu Ltd | 半導体集積回路装置 |
