JPS6419997A - Controller for inverter - Google Patents

Controller for inverter

Info

Publication number
JPS6419997A
JPS6419997A JP62175082A JP17508287A JPS6419997A JP S6419997 A JPS6419997 A JP S6419997A JP 62175082 A JP62175082 A JP 62175082A JP 17508287 A JP17508287 A JP 17508287A JP S6419997 A JPS6419997 A JP S6419997A
Authority
JP
Japan
Prior art keywords
command
mode
operation mode
circuit
outputted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62175082A
Other languages
Japanese (ja)
Inventor
Shigeyuki Sugimoto
Hiroki Ichikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP62175082A priority Critical patent/JPS6419997A/en
Publication of JPS6419997A publication Critical patent/JPS6419997A/en
Pending legal-status Critical Current

Links

Landscapes

  • Control Of Ac Motors In General (AREA)

Abstract

PURPOSE:To prevent promotion of voltage rise in a DC bus, by keeping the voltage command immediately before switching of operating mode as it is. CONSTITUTION:An operation mode determining circuit 12 compares an output frequency command (fo) with a target speed command (fi) to determine an operating mode which is outputted as an operation mode command to an output frequency determining circuit 7, and a timer starting signal is outputted only when an acceleration mode is switched to a steady mode. A timer circuit 13 keeps on outputting an output voltage command hold signal until voltage rise in DC bus due to inertia of load is settled. While the hold signal is inputted, a hold circuit 14 keeps the output voltage command corrected immediately before switching of operation mode.
JP62175082A 1987-07-14 1987-07-14 Controller for inverter Pending JPS6419997A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62175082A JPS6419997A (en) 1987-07-14 1987-07-14 Controller for inverter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62175082A JPS6419997A (en) 1987-07-14 1987-07-14 Controller for inverter

Publications (1)

Publication Number Publication Date
JPS6419997A true JPS6419997A (en) 1989-01-24

Family

ID=15989926

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62175082A Pending JPS6419997A (en) 1987-07-14 1987-07-14 Controller for inverter

Country Status (1)

Country Link
JP (1) JPS6419997A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018182780A (en) * 2017-04-03 2018-11-15 株式会社デンソー Controller of multi-phase rotary machine

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018182780A (en) * 2017-04-03 2018-11-15 株式会社デンソー Controller of multi-phase rotary machine

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