JPS6419976A - Control system of pwm inverter - Google Patents

Control system of pwm inverter

Info

Publication number
JPS6419976A
JPS6419976A JP62173319A JP17331987A JPS6419976A JP S6419976 A JPS6419976 A JP S6419976A JP 62173319 A JP62173319 A JP 62173319A JP 17331987 A JP17331987 A JP 17331987A JP S6419976 A JPS6419976 A JP S6419976A
Authority
JP
Japan
Prior art keywords
frequency
address ports
storage cell
input
pwm
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62173319A
Other languages
Japanese (ja)
Inventor
Masayuki Kogure
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP62173319A priority Critical patent/JPS6419976A/en
Publication of JPS6419976A publication Critical patent/JPS6419976A/en
Pending legal-status Critical Current

Links

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  • Inverter Devices (AREA)

Abstract

PURPOSE:To displace the natural frequency of load driven and the vibrational spectra of noises, and to prevent the generation of noises by changing the relational expression of the frequency of a command wave and the frequency of a carrier wave on specified output frequency. CONSTITUTION:Voltage corresponding to set frequency output from a controller 7 is frequency-converted by a V/F converter 6, and counted by a counter 4 and input to address ports A0-A8 for a storage cell 3. The voltage is A/D converted simultaneously by an A/D converter 5, and input to address ports A9-A12 for the storage cell 3. Outputs D0-D6 corresponding to input values to the address ports are emitted to the storage cell 3, and a switching element controls the number of revolution of a motor 1 by PWM in response to the emission of the outputs D0-D6. Carrier frequency is controlled by inputs to the address ports A9-A12, and the ON/OFF pattern of PWM is determined by force to the address ports A0-A8.
JP62173319A 1987-07-10 1987-07-10 Control system of pwm inverter Pending JPS6419976A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62173319A JPS6419976A (en) 1987-07-10 1987-07-10 Control system of pwm inverter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62173319A JPS6419976A (en) 1987-07-10 1987-07-10 Control system of pwm inverter

Publications (1)

Publication Number Publication Date
JPS6419976A true JPS6419976A (en) 1989-01-24

Family

ID=15958230

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62173319A Pending JPS6419976A (en) 1987-07-10 1987-07-10 Control system of pwm inverter

Country Status (1)

Country Link
JP (1) JPS6419976A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11909344B2 (en) 2020-06-02 2024-02-20 Subaru Corporation Control device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11909344B2 (en) 2020-06-02 2024-02-20 Subaru Corporation Control device

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