JPS6416186A - Video signal processing circuit - Google Patents

Video signal processing circuit

Info

Publication number
JPS6416186A
JPS6416186A JP62173306A JP17330687A JPS6416186A JP S6416186 A JPS6416186 A JP S6416186A JP 62173306 A JP62173306 A JP 62173306A JP 17330687 A JP17330687 A JP 17330687A JP S6416186 A JPS6416186 A JP S6416186A
Authority
JP
Japan
Prior art keywords
ccd
signal
bit
output
transferring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62173306A
Other languages
Japanese (ja)
Inventor
Shigenori Shibue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP62173306A priority Critical patent/JPS6416186A/en
Publication of JPS6416186A publication Critical patent/JPS6416186A/en
Pending legal-status Critical Current

Links

Landscapes

  • Television Signal Processing For Recording (AREA)

Abstract

PURPOSE:To attain the reversing processing of a time base by executing the transferring of an image signal between a pair of CCDs to store the image signal of an integral multiple of 1H and inverting a reading order after the transferring. CONSTITUTION:The image signal inputted through an input circuit 14 to a first CCD 17 is successively transferred from a first to the 910th bit by a transferring clock signal. Next, the all electrodes of 910 bits of the CCD 17 are transferred to a second CCD 21. The electrode of the second CCD 21 is read from the first bit to the 910th bit successively. In the first CCD 17, the next signal of 1H is successively transferred and stored. The output of the second CCD 21 is converted by an output circuit 22 to a voltage and outputted. As an output signal at such a time, the output signal to reverse the time base of the inputted video signal is obtained.
JP62173306A 1987-07-10 1987-07-10 Video signal processing circuit Pending JPS6416186A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62173306A JPS6416186A (en) 1987-07-10 1987-07-10 Video signal processing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62173306A JPS6416186A (en) 1987-07-10 1987-07-10 Video signal processing circuit

Publications (1)

Publication Number Publication Date
JPS6416186A true JPS6416186A (en) 1989-01-19

Family

ID=15958002

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62173306A Pending JPS6416186A (en) 1987-07-10 1987-07-10 Video signal processing circuit

Country Status (1)

Country Link
JP (1) JPS6416186A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0475548U (en) * 1990-11-08 1992-07-01

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0475548U (en) * 1990-11-08 1992-07-01

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