JPS6416024A - Offset correction type analog/digital converter - Google Patents

Offset correction type analog/digital converter

Info

Publication number
JPS6416024A
JPS6416024A JP17138387A JP17138387A JPS6416024A JP S6416024 A JPS6416024 A JP S6416024A JP 17138387 A JP17138387 A JP 17138387A JP 17138387 A JP17138387 A JP 17138387A JP S6416024 A JPS6416024 A JP S6416024A
Authority
JP
Japan
Prior art keywords
output
offset
converter
digital converter
offset correction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17138387A
Other languages
Japanese (ja)
Inventor
Tetsuhiko Kaneaki
Kozo Nuriya
Yasunori Tani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP17138387A priority Critical patent/JPS6416024A/en
Publication of JPS6416024A publication Critical patent/JPS6416024A/en
Pending legal-status Critical Current

Links

Landscapes

  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE:To eliminate an offset by detecting the mean level of output of an A/D (analog digital)converter, and subtracting the value from the A/D converter. CONSTITUTION:The A/D converter 1 converts an analog input VIN into a digital signal DAD, a means level detector 2 receives the digital signal DAD to output its mean level DAU and a subtractor 3 obtains the difference between the digital signal DAD and the mean level DAU. Thus, the output of the subtraction means is used as the A/D conversion output to decrease the offset level of the digital output DO without being affected by the offset of the analog part such as a comparator and the ADC.
JP17138387A 1987-07-09 1987-07-09 Offset correction type analog/digital converter Pending JPS6416024A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17138387A JPS6416024A (en) 1987-07-09 1987-07-09 Offset correction type analog/digital converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17138387A JPS6416024A (en) 1987-07-09 1987-07-09 Offset correction type analog/digital converter

Publications (1)

Publication Number Publication Date
JPS6416024A true JPS6416024A (en) 1989-01-19

Family

ID=15922159

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17138387A Pending JPS6416024A (en) 1987-07-09 1987-07-09 Offset correction type analog/digital converter

Country Status (1)

Country Link
JP (1) JPS6416024A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0479523A (en) * 1990-07-20 1992-03-12 Fujitsu Ltd Offset compensation system for pcm channel unit
EP0483846A2 (en) * 1990-11-02 1992-05-06 Nec Corporation Analog-to-digital converter circuit
EP0589749A1 (en) * 1992-09-25 1994-03-30 Thomson-Csf Analog-digital encoding circuit with zero-offset compensation
WO2004079275A1 (en) 2003-03-05 2004-09-16 Matsushita Electric Industrial Co., Ltd. Heating device and sanitary washing device using the same
JP2007317578A (en) * 2006-05-27 2007-12-06 Sanyo Electric Co Ltd Battery pack
JP2007317579A (en) * 2006-05-27 2007-12-06 Sanyo Electric Co Ltd Battery pack
JP2011172119A (en) * 2010-02-19 2011-09-01 Sony Corp Solid-state image pickup device and camera system

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57203322A (en) * 1981-06-10 1982-12-13 Matsushita Electric Ind Co Ltd Eliminating device of dc component
JPS60145729A (en) * 1984-01-09 1985-08-01 Matsushita Electric Ind Co Ltd Signal clamping method

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57203322A (en) * 1981-06-10 1982-12-13 Matsushita Electric Ind Co Ltd Eliminating device of dc component
JPS60145729A (en) * 1984-01-09 1985-08-01 Matsushita Electric Ind Co Ltd Signal clamping method

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0479523A (en) * 1990-07-20 1992-03-12 Fujitsu Ltd Offset compensation system for pcm channel unit
EP0483846A2 (en) * 1990-11-02 1992-05-06 Nec Corporation Analog-to-digital converter circuit
EP0589749A1 (en) * 1992-09-25 1994-03-30 Thomson-Csf Analog-digital encoding circuit with zero-offset compensation
WO2004079275A1 (en) 2003-03-05 2004-09-16 Matsushita Electric Industrial Co., Ltd. Heating device and sanitary washing device using the same
JP2007317578A (en) * 2006-05-27 2007-12-06 Sanyo Electric Co Ltd Battery pack
JP2007317579A (en) * 2006-05-27 2007-12-06 Sanyo Electric Co Ltd Battery pack
JP2011172119A (en) * 2010-02-19 2011-09-01 Sony Corp Solid-state image pickup device and camera system

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