JPS6415947A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6415947A
JPS6415947A JP17198087A JP17198087A JPS6415947A JP S6415947 A JPS6415947 A JP S6415947A JP 17198087 A JP17198087 A JP 17198087A JP 17198087 A JP17198087 A JP 17198087A JP S6415947 A JPS6415947 A JP S6415947A
Authority
JP
Japan
Prior art keywords
regions
wiring
cell
along
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17198087A
Other languages
Japanese (ja)
Inventor
Yasunori Ouchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP17198087A priority Critical patent/JPS6415947A/en
Publication of JPS6415947A publication Critical patent/JPS6415947A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

PURPOSE:To increase the cell density by annularly placing cell regions and wiring regions in the four triangular sections obtained by partitioning a quadrangular chip with the diagonal lines, along and in parallel with the perimetrical sides, thereby narrowing the width of the wiring regions. CONSTITUTION:The device is provided with a construction in which a quadrangular chip is partitioned into four with the diagonal lins and internal cell regions 1 and wiring regions 2 are placed in the four respective triangular sections along and in parallel with the perimetrical sides, that is, a structure in which cell regions the lengths of which sequentially become shorter from the outermost perimetry to the center are annularly arranged in a quadrangle along the perimetrical sides. The interconnections between the individual cells in the cell regions are uniformized since the wiring regions 2 are also annular as with the cell regions 1, and it is possible to narrow the width of the wiring regions 2. Then, a power supply and grounding wiring pattern 3 is connected to a power supply terminal V and a ground terminal G of an input/output terminal region 4 and provided along the perimeter of the chip and the diagonal lines. Accordingly, the wiring is shortened, the voltage drop decreases, and the operation of the cell circuit is assured.
JP17198087A 1987-07-09 1987-07-09 Semiconductor device Pending JPS6415947A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17198087A JPS6415947A (en) 1987-07-09 1987-07-09 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17198087A JPS6415947A (en) 1987-07-09 1987-07-09 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6415947A true JPS6415947A (en) 1989-01-19

Family

ID=15933304

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17198087A Pending JPS6415947A (en) 1987-07-09 1987-07-09 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6415947A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6516455B1 (en) * 2000-12-06 2003-02-04 Cadence Design Systems, Inc. Partitioning placement method using diagonal cutlines
US6651233B2 (en) 2000-12-06 2003-11-18 Cadence Design Systems, Inc. Method and apparatus for measuring congestion in a partitioned region
US6671864B2 (en) 2000-12-06 2003-12-30 Cadence Design Systems, Inc. Method and apparatus for using a diagonal line to measure an attribute of a bounding box of a net
US6687893B2 (en) 2001-01-19 2004-02-03 Cadence Design Systems, Inc. Method and apparatus for pre-computing routes for multiple wiring models
US6889372B1 (en) 2000-07-15 2005-05-03 Cadence Design Systems Inc. Method and apparatus for routing
US6892371B1 (en) 2002-01-22 2005-05-10 Cadence Design Systems, Inc. Method and apparatus for performing geometric routing
US6951005B1 (en) 2001-06-03 2005-09-27 Cadence Design Systems, Inc. Method and apparatus for selecting a route for a net based on the impact on other nets
US6951006B1 (en) 2002-01-22 2005-09-27 Cadence Design Systems, Inc. Decomposing IC regions and embedding routes

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6889372B1 (en) 2000-07-15 2005-05-03 Cadence Design Systems Inc. Method and apparatus for routing
US6516455B1 (en) * 2000-12-06 2003-02-04 Cadence Design Systems, Inc. Partitioning placement method using diagonal cutlines
US6651233B2 (en) 2000-12-06 2003-11-18 Cadence Design Systems, Inc. Method and apparatus for measuring congestion in a partitioned region
US6671864B2 (en) 2000-12-06 2003-12-30 Cadence Design Systems, Inc. Method and apparatus for using a diagonal line to measure an attribute of a bounding box of a net
US6678872B2 (en) 2000-12-06 2004-01-13 Cadence Design Systems, Inc. Method and apparatus for using a diagonal line to measure congestion in a region of an integrated-circuit layout
US6848091B2 (en) 2000-12-06 2005-01-25 Cadence Design Systems, Inc. Partitioning placement method and apparatus
US6910198B2 (en) 2000-12-06 2005-06-21 Cadence Design Systems, Inc. Method and apparatus for pre-computing and using placement costs within a partitioned region for multiple wiring models
US7100137B2 (en) 2000-12-06 2006-08-29 Cadence Design Systems, Inc. Method and apparatus for quantifying the quality of placement configurations in a partitioned region of an integrated circuit layout
US6687893B2 (en) 2001-01-19 2004-02-03 Cadence Design Systems, Inc. Method and apparatus for pre-computing routes for multiple wiring models
US6951005B1 (en) 2001-06-03 2005-09-27 Cadence Design Systems, Inc. Method and apparatus for selecting a route for a net based on the impact on other nets
US6892371B1 (en) 2002-01-22 2005-05-10 Cadence Design Systems, Inc. Method and apparatus for performing geometric routing
US6951006B1 (en) 2002-01-22 2005-09-27 Cadence Design Systems, Inc. Decomposing IC regions and embedding routes

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