JPS6414993A - Multilayered universal substrate - Google Patents

Multilayered universal substrate

Info

Publication number
JPS6414993A
JPS6414993A JP16989187A JP16989187A JPS6414993A JP S6414993 A JPS6414993 A JP S6414993A JP 16989187 A JP16989187 A JP 16989187A JP 16989187 A JP16989187 A JP 16989187A JP S6414993 A JPS6414993 A JP S6414993A
Authority
JP
Japan
Prior art keywords
layer
penetrated
line
grounding
holes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16989187A
Other languages
Japanese (ja)
Inventor
Kenji Abe
Takeshi Yoshimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP16989187A priority Critical patent/JPS6414993A/en
Publication of JPS6414993A publication Critical patent/JPS6414993A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0286—Programmable, customizable or modifiable circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298—Multilayer circuits

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

PURPOSE:To omit power and grounding wirings, to simplify the arrangement of a bypass capacitor and to improve the reliability of a circuit by a method wherein penetrated holes for mounting IC and penetrated holes for mounting, which come into contact with a power layer and a grounding layer, are provided in a substrate body, which is constituted by laminating the power layer and the grounding layer interposing an intermediate insulating layer between the layers. CONSTITUTION:A universal substrate body 10 is constituted by laminating a power layer 12 and a grounding layer 14 interposing an intermediate insulating layer 13 between the layers. A plurality of pieces of penetrated holes 16a, 16b, 16c, 16d, 26a, 26b, 26c, 26d,... for IC mounting, which penetrate the substrate body between both main surfaces of the substrate body, are bored on the main surfaces; and a plated layer 18b which comes into contact with the power layer 12 is exposed its end parts on the main surfaces in the penetrated holes in the following line (b) adjacent to the penetrated holes in the line (a) of each penetrated hole group, such as 16b-26b...n6b, 17b-27b...n7b, and is connected to a plated layer 18a on the inner surface of each penetrated hole in the line (a) of each penetrated hole group through a solder 19b. Similarly, a plated layer 18c which comes into contact to the grounding layer 14 is exposed its end parts on the main surfaces in the penetrated holes in the line (c) on the previous side adjacent to the line (d) of each penetrated hole group, such as 16c-26c...n6c, 17c-27c...n7c,... and is connected to a plated layer 18d on the inner surface of each penetrated hole in the line (d) of each penetrated hole group through a solder 19c.
JP16989187A 1987-07-09 1987-07-09 Multilayered universal substrate Pending JPS6414993A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16989187A JPS6414993A (en) 1987-07-09 1987-07-09 Multilayered universal substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16989187A JPS6414993A (en) 1987-07-09 1987-07-09 Multilayered universal substrate

Publications (1)

Publication Number Publication Date
JPS6414993A true JPS6414993A (en) 1989-01-19

Family

ID=15894876

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16989187A Pending JPS6414993A (en) 1987-07-09 1987-07-09 Multilayered universal substrate

Country Status (1)

Country Link
JP (1) JPS6414993A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06310870A (en) * 1993-04-21 1994-11-04 Nec Corp Wiring board structure and its manufacture
US5745333A (en) * 1994-11-21 1998-04-28 International Business Machines Corporation Laminar stackable circuit board structure with capacitor

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06310870A (en) * 1993-04-21 1994-11-04 Nec Corp Wiring board structure and its manufacture
US5745333A (en) * 1994-11-21 1998-04-28 International Business Machines Corporation Laminar stackable circuit board structure with capacitor
US6098282A (en) * 1994-11-21 2000-08-08 International Business Machines Corporation Laminar stackable circuit board structure with capacitor

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