JPS6413880A - Sampling pulse generation device for video signal - Google Patents

Sampling pulse generation device for video signal

Info

Publication number
JPS6413880A
JPS6413880A JP62170726A JP17072687A JPS6413880A JP S6413880 A JPS6413880 A JP S6413880A JP 62170726 A JP62170726 A JP 62170726A JP 17072687 A JP17072687 A JP 17072687A JP S6413880 A JPS6413880 A JP S6413880A
Authority
JP
Japan
Prior art keywords
block
signal
video signal
sampling pulse
signals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62170726A
Other languages
Japanese (ja)
Inventor
Shinko Yamada
Masaki Sano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Priority to JP62170726A priority Critical patent/JPS6413880A/en
Publication of JPS6413880A publication Critical patent/JPS6413880A/en
Pending legal-status Critical Current

Links

Landscapes

  • Facsimile Image Signal Circuits (AREA)
  • Television Signal Processing For Recording (AREA)

Abstract

PURPOSE:To obtain a sampling pulse with high stability by allowing a oscillator to obtain signals of which phases are shifted by a prescribed amount and selecting these signals with the aid of a synchronizing signal. CONSTITUTION:The crystal oscillator 1 oscillates with the same frequency as that of the picture element clock of an picture to be an object. A block 20 outputs the signals which the output of the crystal oscillator 1 is delayed by the prescribed amount. A block 21 selects the signal of which phase is the most suitable complying with the horizontal synchronizing signal HSYNC among the four signal generated by the block 20. An A/D converter 23 digitizes a video signal being an analogue signal by making the output of the block 21 as a sampling clock and outputs it.
JP62170726A 1987-07-08 1987-07-08 Sampling pulse generation device for video signal Pending JPS6413880A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62170726A JPS6413880A (en) 1987-07-08 1987-07-08 Sampling pulse generation device for video signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62170726A JPS6413880A (en) 1987-07-08 1987-07-08 Sampling pulse generation device for video signal

Publications (1)

Publication Number Publication Date
JPS6413880A true JPS6413880A (en) 1989-01-18

Family

ID=15910253

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62170726A Pending JPS6413880A (en) 1987-07-08 1987-07-08 Sampling pulse generation device for video signal

Country Status (1)

Country Link
JP (1) JPS6413880A (en)

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