JPS5444432A - Generator of sampled clock pulse - Google Patents

Generator of sampled clock pulse

Info

Publication number
JPS5444432A
JPS5444432A JP11072277A JP11072277A JPS5444432A JP S5444432 A JPS5444432 A JP S5444432A JP 11072277 A JP11072277 A JP 11072277A JP 11072277 A JP11072277 A JP 11072277A JP S5444432 A JPS5444432 A JP S5444432A
Authority
JP
Japan
Prior art keywords
signal
circuit
phase
clock pulse
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11072277A
Other languages
Japanese (ja)
Inventor
Kaneyoshi Sugawa
Takao Nakamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP11072277A priority Critical patent/JPS5444432A/en
Publication of JPS5444432A publication Critical patent/JPS5444432A/en
Pending legal-status Critical Current

Links

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

PURPOSE: To produce clock pulse from the horizontal synchronizing signal independently of color or monochrome, by applying the output of the oscillation circuit of which frequency is controlled with the horizontal synchronizing signal to the variable phase shifter controlled with the burst signal.
CONSTITUTION: The horizontal synchronizing signal b is separated 1 and picked up from the input 11 forizontal video signal a, the phase is compared with the signal e in 15MHz at the phase comparison circuit 4, and the DC voltage in response to the phase difference controls the oscillation frequency of the oscillation circuit 5. On the other hand, the burst signal c picked up 2 is converted 3 into the burst pulse signal d and is fed to the phase comparison circuit 9, where the output of the circuit 5 is frequency-divided into 1/4 (waveform f) and the phase comparison 9 is made with the signal g fed via the variable phase shifter 8, and the phase shifter 8 is controlled according to the difference. Accordinly, the signal g is multiplied by n with the multiplying circuit 10 by making agreement the phases of the signal g and d, and the clock pulse h for sampling can be obtained from the output termimal 12.
COPYRIGHT: (C)1979,JPO&Japio
JP11072277A 1977-09-14 1977-09-14 Generator of sampled clock pulse Pending JPS5444432A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11072277A JPS5444432A (en) 1977-09-14 1977-09-14 Generator of sampled clock pulse

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11072277A JPS5444432A (en) 1977-09-14 1977-09-14 Generator of sampled clock pulse

Publications (1)

Publication Number Publication Date
JPS5444432A true JPS5444432A (en) 1979-04-07

Family

ID=14542819

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11072277A Pending JPS5444432A (en) 1977-09-14 1977-09-14 Generator of sampled clock pulse

Country Status (1)

Country Link
JP (1) JPS5444432A (en)

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