JPS6413757A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPS6413757A
JPS6413757A JP62170122A JP17012287A JPS6413757A JP S6413757 A JPS6413757 A JP S6413757A JP 62170122 A JP62170122 A JP 62170122A JP 17012287 A JP17012287 A JP 17012287A JP S6413757 A JPS6413757 A JP S6413757A
Authority
JP
Japan
Prior art keywords
time
transistor
power supply
turned
potential
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62170122A
Other languages
Japanese (ja)
Other versions
JP2787918B2 (en
Inventor
Michihiro Yamada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP62170122A priority Critical patent/JP2787918B2/en
Publication of JPS6413757A publication Critical patent/JPS6413757A/en
Application granted granted Critical
Publication of JP2787918B2 publication Critical patent/JP2787918B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Dram (AREA)

Abstract

PURPOSE:To improve characteristics at the time when a power supply is turned ON by a method wherein a first transistor is kept conductive for a fixed time after the power supply is turned ON, an output terminal for a substrate bias generating circuit is clamped forcibly at 0V a second transistor is kept conductive after the fixed time passes and the working of the substrate bias generating circuit is transmitted to the output terminal. CONSTITUTION:When a power supply VCC is turned at the time S0, the power supply VCC rises toward a specified potential level during the time from the time S0 to the time S2. Potential VP1 at a node P1 follows to the rise of the power supply VCC by the capacitive coupling of a capacitor CA after the time S0. Substrate bias potential VBB is also elevated gradually by the capacitive coupling of a parasitic capacitor CT. When potential VP1 exceeds the threshold voltage VTH of a transistor Q1 at the time S1, the transistor Q1 becomes conductive, thus short-circuiting a VSS wiring 2 and a VBB wiring 4, then forcibly clamping potential VBB at 0V. A pulse signal POR rises at the time S4 and exceeds the threshold voltage of a transistor Q2 up to the time S5, thus making the transistor Q2 conductive. Accordingly, characteristics at the time when the power supply is turned ON can be improved.
JP62170122A 1987-07-07 1987-07-07 Semiconductor integrated circuit device Expired - Lifetime JP2787918B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62170122A JP2787918B2 (en) 1987-07-07 1987-07-07 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62170122A JP2787918B2 (en) 1987-07-07 1987-07-07 Semiconductor integrated circuit device

Publications (2)

Publication Number Publication Date
JPS6413757A true JPS6413757A (en) 1989-01-18
JP2787918B2 JP2787918B2 (en) 1998-08-20

Family

ID=15899050

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62170122A Expired - Lifetime JP2787918B2 (en) 1987-07-07 1987-07-07 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JP2787918B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04188665A (en) * 1990-11-19 1992-07-07 Matsushita Electric Ind Co Ltd Semiconductor device
US6205079B1 (en) 1999-05-25 2001-03-20 Kabushiki Kaisha Toshiba Semiconductor integrated circuit having power-supply circuits for producing internal supply voltages
JP2006120201A (en) * 2004-10-19 2006-05-11 Matsushita Electric Ind Co Ltd Dropped voltage output circuit
JP2006190435A (en) * 2004-12-28 2006-07-20 Hynix Semiconductor Inc Internal voltage generator for semiconductor memory device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60117655A (en) * 1983-11-16 1985-06-25 インモス、コーポレーシヨン Method and device for controlling latchup of cmos circuit
JPS6195561A (en) * 1984-10-17 1986-05-14 Fujitsu Ltd Semiconductor integrated circuit
JPS6248061A (en) * 1985-08-26 1987-03-02 シ−メンス、アクチエンゲゼルシヤフト Integrated circuit by complementary circuit technology

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60117655A (en) * 1983-11-16 1985-06-25 インモス、コーポレーシヨン Method and device for controlling latchup of cmos circuit
JPS6195561A (en) * 1984-10-17 1986-05-14 Fujitsu Ltd Semiconductor integrated circuit
JPS6248061A (en) * 1985-08-26 1987-03-02 シ−メンス、アクチエンゲゼルシヤフト Integrated circuit by complementary circuit technology

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04188665A (en) * 1990-11-19 1992-07-07 Matsushita Electric Ind Co Ltd Semiconductor device
US6205079B1 (en) 1999-05-25 2001-03-20 Kabushiki Kaisha Toshiba Semiconductor integrated circuit having power-supply circuits for producing internal supply voltages
JP2006120201A (en) * 2004-10-19 2006-05-11 Matsushita Electric Ind Co Ltd Dropped voltage output circuit
JP2006190435A (en) * 2004-12-28 2006-07-20 Hynix Semiconductor Inc Internal voltage generator for semiconductor memory device

Also Published As

Publication number Publication date
JP2787918B2 (en) 1998-08-20

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