KR920003846B1 - Back bias shunt circuit of semiconductor memory apparatus - Google Patents

Abstract

The back-bias generating circuit for preventing a latch-up of a CMOS device upon power-on comprises a shunt circuit. The shunt circuit comprises a node (20), a means (60) for supplying power voltage to the node under the control of a signal for sensing the application of power voltage, an output means (40) (59) for delaying the sensing signal to output the delayed signal, the sensing signal having a predetermined pulse width, a discharging means (70) for discharging the potential of the node into a low level under the control of the output means (40,59), a discharging means (90) for discharging a back-bias voltage into a ground level under the control of the voltage state of the node (20) and a means (80) for connecting the back-bias voltage to the node.

Description

Back bias shunt circuit of semiconductor memory device

1A is a block diagram of a conventional back bias voltage generation circuit.

1B is a conventional shunt circuit.

2 is a circuit diagram of the present invention.

3a is a VBB waveform diagram without shunt circuit.

3b is a waveform diagram according to the invention.

* Explanation of symbols for main parts of the drawings

30: back bias voltage generation circuit (VBB generation circuit) 40: delay circuit

50: pulse shaping circuit 80: VBB connection circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a back bias generation circuit of a semiconductor memory device, and more particularly, to a back bias shunt circuit capable of preventing a latch-up phenomenon of a CMOS device at power-on.

In CMOS devices, since the threshold voltage is changed due to the bias between the source and the substrate during operation, the device characteristics are affected. In a general dynamic lead write memory device (DRAM), a negative voltage, that is, a back bias, is supplied to a substrate. I'm using the method.

The back bias generation circuit basically senses the level of the back bias VBB to allow the oscillator to generate a voltage of a predetermined frequency, and accordingly pump or clamp the back bias voltage to maintain a constant level.

The form of the back bias generation circuit is disclosed in US Pat. Nos. 4,631,421, 4,115,710 and 4,494,223.

The back bias generation circuit (or substrate bias generation circuit) disclosed in the above-mentioned 4,631,421 employs a shunt circuit for preventing a latchup phenomenon occurring in an integrated circuit employing CMOS in addition to the above-described basic components.

The latch-up phenomenon is a phenomenon unique to CMOS devices. When a certain change is received from the outside, this state is maintained as long as an overcurrent flows between the power supply and the ground and the power supply voltage is turned off once. do.

For example, in an internal substrate of a CMOS inverter composed of a PMOS trap transistor and an NMOS transistor, the PN junction has a plurality of PN junctions between the substrate and the active region (source or drain region). Both sides of the pnp transistor.

Parasitic bipolar transistors do not operate because all pn junctions are reverse biased in the normal operation state of CMOS devices, but if the pn junction is in reverse biased state in the normal state, it becomes forward biased or excessive Current flows into the silicon substrate to cause a potential difference (back bias coupling level or substrate bias coupling level), which eventually causes the parasitic bipolar transistors to be in a conductive state, causing a latchup phenomenon.

Therefore, in order to prevent the latch-up phenomenon, a shunt operation is required to bring the back bias voltage Vbb to the ground level at power-on.

FIG. 1A is a configuration diagram of a back bias generation circuit (or substrate bias generation circuit) having a conventional shunt circuit, which is disclosed in US Patent No. 4,631,421, wherein the shunt circuit is shown in FIG. 1B. The circuit is shown.

In the back bias voltage generating circuit of FIG. 1A, the oscillator 2 receiving the back bias (hereinafter referred to as Vbb) feedback signal output from the back bias sensing circuit 1 changes its frequency according to the Vbb level state (VBB is On the negative side, a low frequency shift) signal is output to the first and second pump circuits 3 and 4, and the first and second pump circuits 3 and 4 perform a voltage pimping operation using a capacitor. Outputs the high level VBB voltage. As a result, the VBB voltage of the bias node 8 is charged or discharged.

Meanwhile, an input terminal of the first pump circuit 3 and an internal pumping node are connected to the shunt circuit 7, and the input of the second pump circuit 4 is controlled by the reset voltage sensing circuit 5, and the clamp The circuit 6 clamps the VBB level.

The shunt circuit 7 causes the VBB to go to the ground level through the shunt transistor 50 controlled by the output state of the inverter 51, as shown in FIG. 1 (b).

That is, the shunt transistor 50 operates when the node 52 is "high" and the node 53 is "low", and the node 21 which is an output line of the oscillator 2 is operated by the oscillator 2. Transitions into the "low" and "high" states, and the pumping node 25 of the first pump circuit 3 of FIG. 1 (a) has a swing width from OV to -Vcc.

The shunt operation here is a PMOS transistor having a large resistance component when the node 53 is in OV before power-on and the oscillator 2 is operated and the potential of the node 21 becomes "low" after power-on. A capacitor 54 having a large capacity is charged through the capacitor 56 to slightly increase the potential of the node 53.

When the charge voltage of the capacitor 54 rises to the threshold hold voltage of the NMOS transistor of the inverter 51, the output of the inverter 51 interrupts the shunt transistor 50 to stop the shunt function.

In addition, when the NMOS transistor of the inverter 51 becomes conductive, the voltage of the node 52 is transmitted to the node 58. At this time, the voltage of the node 52 is diode-connected transistor 57 while the oscillator 2 is operated. Since the potential of the node 52 has a value of -V _CC + V _TN which is lower than VBB, the shunt transistor 50 is completely "turned off" so that the shunt function is disabled.

The operation of the conventional shunt circuit as described above has the following problems.

First, the initial state, that is, when there is no output of the oscillator, is that the potential of the node 53 does not become OV but is in a floating state. This is a common phenomenon in the input / output line or data bus of a memory circuit when there is no specific precharge means.

Secondly, since the shunt timing depends on the time when the capacitor 54 is charged toward the VCC level through the PMOS transistor 56 conducted by the output " low " of the oscillator 2, the shunt operation is performed. The time depends on the size of the PMOS transistor 56 and the capacity of the capacitor 54. In other words, in order to operate the shunt circuit for a few kVs or more after power-on, the length of the PMOS transistor 56 must be very large and the size of the capacitor 54 must be very large. This is an obstacle to the integrated drawing on the circuit.

Thirdly, when the voltage of the node 53 has an ambiguous potential near about Vcc, the first pump circuit of Fig. 1 (a) is passed through the transistor 57 diode-connected by a direct current path through the inverter 51. The pumping node of (3) can be charged up.

That is, since the inverter flows a large DC current in the transition band from the "low" state to the "high" state, this causes the charge-up phenomenon of the pimping node, thereby preventing the V _BB level from having a constant voltage.

Accordingly, an object of the present invention is to provide a circuit capable of preventing a latch-up phenomenon caused by a pn junction between a substrate and an active region generated during power-up in a CMOS device and enabling a more efficient and stable back bias voltage shunt operation.

In order to achieve the object of the present invention, the present invention is controlled by a signal for detecting the application of the power supply voltage means for supplying a power supply voltage to the node, delaying the signal for detecting the application of the power supply voltage and a predetermined pulse Means for outputting to have a width, means for discharging the potential of the node to a low level controlled by the output of the means, and controlled by the voltage state of the node to discharge the back bias voltage to ground level. Means for ignoring, means for discharging a back bias voltage to ground level controlled by the voltage state of the node, and means for connecting the back bias voltage to the node controlled by the voltage state of the node. And a configured back bias shunt circuit.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2 is a shunt circuit of the present invention. The shunt circuit is input by the VBB generation circuit 30 and three inverters 41-42 connected in series by inputting a signal VccH sensed when the power supply voltage Vcc is powered up (state transitioned from low level to high level). The delay circuit 40 for outputting the delayed and inverted signals and the output signal of the delay circuit 40 are branched and delayed and inverted by only three inverters 61-63. A pulse width shaping circuit 59 for outputting through the inverter 65 and inverting the output by the inverter 65, and a P-type insulated gate field effect transistor having a drain or source connected to a power supply voltage Vcc and receiving the power-up detection signal VccH as a gate (Hereinafter, IGFET) 60 and a drain or a source are connected to a source or a drain of the P-type IGFET 60 and a gate is connected to an output node 10 of the pulse width shaping circuit 59, and a source or a drain is connected. P-grounded IGFET An inverter 81 having an input terminal connected to a node 20 between the P-type IGFETs 60 and 70 and a gate connected to an output terminal of the inverter 81 and a drain of the VBB generation circuit A VBB transfer circuit 80 composed of an n-type IGFET 82 connected to the node 30 and a source connected to the node 20, and a gate of the node 20 connected to the drain of the n-type IGFET 82; And an n-type IGFET 90 having a drain connected to the VBB generation circuit 30 and a source grounded together.

FIG. 3 (a) shows the VBB waveform latched up due to pn junction in the substrate at power-up when there is no shunt circuit. FIG. 3 (b) shows waveforms according to the operation of the shunt circuit of FIG. It is also.

In (a) and (b) of FIG. 3, reference character (a) denotes a power supply voltage Vcc, (b) denotes a power-up detection signal VccH, (c) denotes a potential of the node 10, and (d) (E) represents the back bias voltage VBB, and reference numerals C1 and C2 of the VBB waveform (e) in FIG. 3 (a) indicate the case where the pumping capacity is small and large, respectively. will be.

The operation of the shunt circuit according to the present invention will now be described with reference to the second and third (a) and (b) figures.

Referring first to the state of VBB in the absence of a shunt circuit with reference to FIG. 3 (a), when the power supply voltage Vcc starts to go to a high level as shown in FIG. Power-up time) As mentioned above, a Pn ⁺ junction region is formed between the P-type substrate and the n + -type active region, and the junction region voltage rises to the cut-in voltage (-0.6 V) of the diode. The parasitic bipolar transistors present in the P-type substrate are " turned on " to cause a latchup phenomenon.

On the other hand, in the shunt circuit of FIG. 2, when Vcc is powered up, the power-up detection signal VccH becomes " high " when the Vcc rises above the firing level to turn off the P-type IGFET 60. FIG.

On the other hand, the VccH signal appears as a "low" state signal having a pulse width of about several tens ns at the node 10 by the pulse width shaping circuit 59 after a predetermined time delay through the delay circuit 40, which is P The type IGFET 70 is turned on.

Since the P-type IGFET 60 is in a non-conducting state, the potential of the node 20 goes from "high" to "low" state, which causes the gate voltage of the n-type IGFET 82 to be "low" to "high" state. To go to.

The potential of the node 10 transitions from "high" to "low" because the voltage of the node 10 is discharged near the ground by the conduction of the P-type IGFET 70. Therefore, the n-type IGFET 90 connected between the VBB generation circuit 30 and the ground is turned on until the potential of the node 10 goes to the "low" state, so that the VBB can be brought to the ground level. That is, it clamps VBB to 0V.

When the potential of the node 20 is at the "low" level and the n-type IGFET 82 is turned on to deliver VBB to the node 20, the n-type IGFET 90 is turned off so that the shunt function is terminated. do.

However, when the VBB level rises again, the potential of the node 20 becomes high, which may turn the n-type IGFET 90 on again to discharge the VBB. That is, the VBB can be clamped to OV even when the VBB level rises after the VccH signal is enabled. If the VBB falls below OV, the gate voltage of the n-type IGFET 90 is low and is sufficiently turned off.

Accordingly, it can be seen from waveform (e) of FIG. 3 (b) that the VBB is quickly clamped to OV at the beginning of the power-up by the operation of the shunt circuit of FIG. 2 and no rise above OV occurs even after the power-up.

Referring to FIG. 3 (b), when the P-type IGFET 70 is turned on with the rising edge of the node 10 having a "low" signal level of several tens of ns pulse width by the rising edge when the VccH signal is enabled, The potential at node 20 transitions from " high " to " low ", so that the VBB transitions below OV.

As described above, the present invention prevents the latch-up phenomenon peculiar to CMOS devices by clamping the VBB level to OV at power-on by using a shunt circuit in semiconductor and memory devices, and making the VBB level changing even after power-up below OV. It can be effective.

In addition, the present invention has an advantage that the operation timing of the shunt circuit can be easily adjusted by using the power-up detection signal in the method of clamping the VBB level below OV.

Claims (3)

In a back bias circuit of a semiconductor memory device, a node (60), means (60) for supplying a power supply voltage to the node (20) controlled by a signal for sensing application of a power supply voltage, and application of the power supply voltage Means 40 and 59 for delaying a signal for detecting the signal and outputting the pulse signal having a predetermined pulse width and outputting the potential of the node 20. A means 70 for discharging to a low level, a means 90 for discharging a back bias voltage to ground level controlled by the voltage state of the node 20, and a voltage state of the node 20 And a back bias shunt circuit configured by means (80) for controlling the back bias voltage to connect the back bias voltage to the node (20). 2. The back bias circuit of claim 1, wherein the means (80) operates at least after enabling the means (70). A back bias circuit according to claim 1, wherein said means (90) operates before enabling said means (70).

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