KR910012935A - Back bias shunt circuit of semiconductor memory device - Google Patents

Back bias shunt circuit of semiconductor memory device Download PDF

Info

Publication number
KR910012935A
KR910012935A KR1019890020598A KR890020598A KR910012935A KR 910012935 A KR910012935 A KR 910012935A KR 1019890020598 A KR1019890020598 A KR 1019890020598A KR 890020598 A KR890020598 A KR 890020598A KR 910012935 A KR910012935 A KR 910012935A
Authority
KR
South Korea
Prior art keywords
back bias
node
memory device
semiconductor memory
voltage
Prior art date
Application number
KR1019890020598A
Other languages
Korean (ko)
Other versions
KR920003846B1 (en
Inventor
유제환
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019890020598A priority Critical patent/KR920003846B1/en
Publication of KR910012935A publication Critical patent/KR910012935A/en
Application granted granted Critical
Publication of KR920003846B1 publication Critical patent/KR920003846B1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/16—Protection against loss of memory contents

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)

Abstract

내용 없음.No content.

Description

반도체 메모리장치의 백바이어스 션트회로Back bias shunt circuit of semiconductor memory device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명의 회로도.2 is a circuit diagram of the present invention.

제3(A)도는 션트회로가 없을때의 VBB파형도.3A shows the VBB waveform when there is no shunt circuit.

제3(B)도는 본 발명에 따른 파형도.3B is a waveform diagram according to the present invention.

Claims (3)

반도체 메모리장치의 백바이어스회로에 있어서, 노드(20)와, 전원전압의 인가를 감지하는 신호에 의해 제어되어 상기 노드(20)에 전원전압을 공급하는 수단(60)과, 상기 전원전압의 인가를 감지하는 신호를 지연시키고 소정의 펄스폭을 갖도록 하여 출력시키는 수단(40)(50)과, 상기 수단(40)(50)의 출력에 의해 제어되어 상기 노드(20)의 전위를 접지레벨로 디스차이지하는 수단(70)과, 사이 노드(20)의 전압상태에 의해 제어되어 백바이어스 전압을 접지레벨로 디스차아지 하는 수단(90)과, 상기 노드(20)의 전압상태에 의해 제어되어 상기 백바이어스전압을 상기 노드(20)로 연결시켜 주는 수단(80)으로 구성된 백바이어스 션트회로를 구비함을 특징으로 하는 반도체 메모리장치의 백바이어스회로.In a back bias circuit of a semiconductor memory device, a node (60), means (60) for supplying a power supply voltage to the node (20) controlled by a signal for sensing application of a power supply voltage, and application of the power supply voltage Means 40 and 50 for delaying a signal for detecting the signal and having a predetermined pulse width, and controlling the output of the means 40 and 50 to bring the potential of the node 20 to a ground level. Controlled by means of the discharging means 70, voltage state of the internode 20, means of discharging the back bias voltage to ground level, and controlled by the voltage state of the node 20 And a back bias shunt circuit comprising means (80) for connecting said back bias voltage to said node (20). 제1항에 있어서, 상기 수단(80)이 최소한 상기 수단(70)의 인에이블 이후에 동작함을 특징으로 하는 반도체 메모리장치의 백바이어스회로.2. The back bias circuit of claim 1, wherein the means (80) operates at least after enabling the means (70). 제1항에 있어서, 상기 수단(90)이 상기 수단(70)의 인에이블전에 동작함을 특징으로 하는 반도체 메모리장치의 백바이어스회로.2. A back bias circuit according to claim 1, wherein said means (90) operates before enabling said means (70). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019890020598A 1989-12-30 1989-12-30 Back bias shunt circuit of semiconductor memory apparatus KR920003846B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019890020598A KR920003846B1 (en) 1989-12-30 1989-12-30 Back bias shunt circuit of semiconductor memory apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019890020598A KR920003846B1 (en) 1989-12-30 1989-12-30 Back bias shunt circuit of semiconductor memory apparatus

Publications (2)

Publication Number Publication Date
KR910012935A true KR910012935A (en) 1991-08-08
KR920003846B1 KR920003846B1 (en) 1992-05-15

Family

ID=19294642

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890020598A KR920003846B1 (en) 1989-12-30 1989-12-30 Back bias shunt circuit of semiconductor memory apparatus

Country Status (1)

Country Link
KR (1) KR920003846B1 (en)

Also Published As

Publication number Publication date
KR920003846B1 (en) 1992-05-15

Similar Documents

Publication Publication Date Title
KR960035634A (en) Self refresh cycle controller
KR910013531A (en) Electrostatic Discharge Protection Circuit for Integrated Circuits
KR910016133A (en) Semiconductor integrated circuit
KR890004486A (en) Buffer circuit
KR920008768A (en) Semiconductor memory device
KR970029752A (en) Internal boost power generation circuit of semiconductor memory device
TW346629B (en) Semiconductor memory device
KR870008239A (en) Automatic power control
KR920000068A (en) Integrated power supply monitor circuit
KR900002304A (en) Semiconductor memory
DE3689322D1 (en) Power-on reset circuitry.
KR910019050A (en) Semiconductor memory
KR850005917A (en) Power On / Off Control Circuit
KR870007512A (en) Semiconductor integrated circuit with circuit for detecting address signal change
KR880011920A (en) Semiconductor integrated circuit with input protection circuit
KR910012974A (en) Card type semiconductor device
KR910012935A (en) Back bias shunt circuit of semiconductor memory device
KR960025707A (en) Step-up circuits used in active cycles of semiconductor memory devices
KR960043523A (en) Data output buffer with clamp
JPS54142987A (en) Protecting method from overdrive of semiconductor laser
KR930024018A (en) Semiconductor devices
KR960015569A (en) Apparatus and method for powering up using a counter-enabled driver
KR910013276A (en) Semiconductor integrated circuit device
KR910013275A (en) Power Sup Stability Circuit of Semiconductor Device
KR970051088A (en) Internal power supply voltage supply circuit of semiconductor memory device

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20010409

Year of fee payment: 10

LAPS Lapse due to unpaid annual fee