KR910013275A - Power Sup Stability Circuit of Semiconductor Device - Google Patents

Power Sup Stability Circuit of Semiconductor Device Download PDF

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Publication number
KR910013275A
KR910013275A KR1019890020609A KR890020609A KR910013275A KR 910013275 A KR910013275 A KR 910013275A KR 1019890020609 A KR1019890020609 A KR 1019890020609A KR 890020609 A KR890020609 A KR 890020609A KR 910013275 A KR910013275 A KR 910013275A
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KR
South Korea
Prior art keywords
power supply
circuit
back bias
detection signal
supply voltage
Prior art date
Application number
KR1019890020609A
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Korean (ko)
Other versions
KR930002573B1 (en
Inventor
유제환
Original Assignee
김광호
삼성전자 주식회사
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Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019890020609A priority Critical patent/KR930002573B1/en
Publication of KR910013275A publication Critical patent/KR910013275A/en
Application granted granted Critical
Publication of KR930002573B1 publication Critical patent/KR930002573B1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type

Abstract

내용 없음.No content.

Description

반도체 소자의 파워엎 안정회로Power Sup Stability Circuit of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3(A)도는 본 발명에 따른 구성도,3 (A) is a configuration diagram according to the present invention,

제3(B)도는 제3(A)도에 의한 전압상태도,3 (B) is a voltage state diagram according to FIG. 3 (A),

제3(C)도는 VccH 발생회로도.3C is a VccH generation circuit diagram.

Claims (5)

고집적 반도체 메모리장치의 파워엎 안정회로에 있어서, 전원전압인가(또는 파워엎)와 동시에 구동되는 전원전압 감지신호 발생회로(30)와 셀플레이트 및 비트라인 프리차아지 회로(10)와 백바이어스 전압 발생회로(20)와, 상기 전원전압 감지신호 발생신호(30)의 출력신호인 전원전압 감지신호에 의해 구동되는 백바이어스 선트회로(60)와, 상기 전원전압 감지신호 발생회로(30)의 출력신호인 전원전압 감지신호와 상기 백바이어스 전압 발생회로(20)의 백바이어스 전압의 상태에 의해 백바이어스 레벨 감지신호를 출력하여 어드레스 스트로브 회로(60)로 인가하는 백바이어스 레벨 감지회로(50)로 구성됨을 특징으로 하는 파워엎 안정회로.In a power supply stabilization circuit of a highly integrated semiconductor memory device, a power supply voltage sensing signal generating circuit 30, a cell plate and a bit line precharge circuit 10, and a back bias voltage are driven simultaneously with a power supply voltage (or power supply). An output of the generation circuit 20, the back bias circuit 60 driven by the power supply voltage detection signal which is the output signal of the power supply voltage detection signal generation signal 30, and the output of the power supply voltage detection signal generation circuit 30. The back bias level detection circuit 50 outputs the back bias level detection signal to the address strobe circuit 60 based on the power supply voltage detection signal and the back bias voltage of the back bias voltage generation circuit 20. Power shut down stability circuit, characterized in that configured. 제1항에 있어서, 상기 전원전압 감지신호 발생회로(30)가 상기 전원전압이 소정레벨 이상이 되었을때 전원전압 감지신호를 인에이블시킴을 특징으로 하는 파워엎 안정회로.The power supply stabilization circuit according to claim 1, wherein the power supply voltage detection signal generation circuit (30) enables the power supply voltage detection signal when the power supply voltage becomes higher than a predetermined level. 제1항 또는 제2항에 있어서, 상기 백바이어스 선트회로(60)가 상기 전원전압 감지신호가 인에이블 되기전에는 백바이어스 전압을 0V로 클램핑하고, 상기 전원전압 감지신호가 인에이블된 후에는 상기 백바이어스 전압을 백바이어스 레벨로 끌어내림을 특징으로 하는파워엎 안정회로.The back bias shunt circuit 60 is configured to clamp the back bias voltage to 0V before the power supply voltage detection signal is enabled, and after the power supply voltage detection signal is enabled. A power stabilized circuit characterized by bringing the back bias voltage down to the back bias level. 제1항에 있어서, 상기 백바이어스 레벨 감지회로(50)가 백바이어스전압이 0V로 부터 소정레벨 이하로 강하되었을 때 백바이어스 감지신호를 인에이블 시킴을 특징으로 하는 파워엎 안정회로.The power supply stabilization circuit according to claim 1, wherein the back bias level detection circuit (50) enables the back bias detection signal when the back bias voltage drops from 0V to a predetermined level or less. 제1항 또는 제3항에 있어서, 상기 어드레스 스트로브 회로(60)가 상기 백바이어스 감지신호가 인에이블되기 전에는 어드레스 스트로브 신호들은 프리차아지하고,, 상기 백바이어스 감지신호가 인에이블된 후에는 상기 어드레스 스트로브 신호들을 구동시킴을 특징으로 하는 파워엎 안정회로.4. The method of claim 1 or 3, wherein the address strobe circuit 60 precharges the address strobe signals before the back bias detection signal is enabled, and after the back bias detection signal is enabled. A power-supply stabilizer circuit for driving address strobe signals. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019890020609A 1989-12-30 1989-12-30 Power-up stabilization circuit of semiconductor KR930002573B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019890020609A KR930002573B1 (en) 1989-12-30 1989-12-30 Power-up stabilization circuit of semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019890020609A KR930002573B1 (en) 1989-12-30 1989-12-30 Power-up stabilization circuit of semiconductor

Publications (2)

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KR910013275A true KR910013275A (en) 1991-08-08
KR930002573B1 KR930002573B1 (en) 1993-04-03

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Application Number Title Priority Date Filing Date
KR1019890020609A KR930002573B1 (en) 1989-12-30 1989-12-30 Power-up stabilization circuit of semiconductor

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KR (1) KR930002573B1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100403341B1 (en) * 2001-08-24 2003-11-01 주식회사 하이닉스반도체 Power-up signal generation circuit
KR100734076B1 (en) * 2001-10-23 2007-07-02 매그나칩 반도체 유한회사 Initialize and power up signal generator

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100403341B1 (en) * 2001-08-24 2003-11-01 주식회사 하이닉스반도체 Power-up signal generation circuit
KR100734076B1 (en) * 2001-10-23 2007-07-02 매그나칩 반도체 유한회사 Initialize and power up signal generator

Also Published As

Publication number Publication date
KR930002573B1 (en) 1993-04-03

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