JPS6413483A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPS6413483A
JPS6413483A JP62168661A JP16866187A JPS6413483A JP S6413483 A JPS6413483 A JP S6413483A JP 62168661 A JP62168661 A JP 62168661A JP 16866187 A JP16866187 A JP 16866187A JP S6413483 A JPS6413483 A JP S6413483A
Authority
JP
Japan
Prior art keywords
signal
circuit
test
aging
logic part
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62168661A
Other languages
Japanese (ja)
Inventor
Masatoshi Kawashima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP62168661A priority Critical patent/JPS6413483A/en
Publication of JPS6413483A publication Critical patent/JPS6413483A/en
Pending legal-status Critical Current

Links

Landscapes

  • Testing Of Individual Semiconductor Devices (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

PURPOSE:To facilitate aging by providing a test signal generating circuit which is combined effectively for the aging and generates a test signal and a signal selecting circuit which transmits the test signal selectivity to a logic part. CONSTITUTION:The logic part LC is supplied with an input signal normally through external terminals S1-Si. The test signal generating circuit is provided which consists of an oscillation circuit OSC composed of a ring oscillator and a frequency dividing circuit FD. The circuit OSC is put in operation selectively according to an aging test signal AT supplied through an external terminal AT. At this time, an oscillation signal g0 generated by the circuit OSC is frequency-divided and edited to generate test signals g1-gi which are most effective for an aging test. A signal selecting circuit SEL is provided between input buffers IB1-IB3, and the logic part LC, and sends the input signal supplied through the terminals S1-Si or the signals g1-gi to the logic part LC selectively according to the signal AT.
JP62168661A 1987-07-08 1987-07-08 Semiconductor integrated circuit device Pending JPS6413483A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62168661A JPS6413483A (en) 1987-07-08 1987-07-08 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62168661A JPS6413483A (en) 1987-07-08 1987-07-08 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPS6413483A true JPS6413483A (en) 1989-01-18

Family

ID=15872157

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62168661A Pending JPS6413483A (en) 1987-07-08 1987-07-08 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS6413483A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01227081A (en) * 1988-03-07 1989-09-11 Sharp Corp Semiconductor integrated circuit
CN115166462A (en) * 2022-07-04 2022-10-11 赖俊生 Method, device and equipment for continuously monitoring full life cycle of semiconductor

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01227081A (en) * 1988-03-07 1989-09-11 Sharp Corp Semiconductor integrated circuit
CN115166462A (en) * 2022-07-04 2022-10-11 赖俊生 Method, device and equipment for continuously monitoring full life cycle of semiconductor
CN115166462B (en) * 2022-07-04 2023-08-22 赖俊生 Method, device and equipment for continuously detecting full life cycle of semiconductor chip

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